Low frequency digital phase measuring instrument based on AVR microcontroller and FPGA

Abstract: A system design scheme based on AVR ATmega128 microcontroller and Altera's Cyclone series EP1C3T100 is proposed. The measurement principle and measurement error of the digital low-frequency phase meter and the method of eliminating them are analyzed. The powerful computing and control functions of the microcontroller and the fast computing speed and rich resources of FPGA are utilized. The software and hardware design of the system is mainly introduced. Practice shows that the phase meter designed in this scheme can accurately measure the frequency and phase difference of low-frequency sine wave signals, and has the advantages of fast processing speed, stable and reliable, and high accuracy.
Keywords: digital phase meter; microcontroller; FPGA; error; frequency; phase difference

Low-frequency digital phase meters are often used in the industrial field to accurately measure the phase difference between two signals. For example, they are widely used in power systems, frequency characteristics research, laser ranging and other fields. The accuracy of phase detection directly determines the overall performance of the system. This requires the measuring instrument to gradually develop in the direction of intelligence and test automation. This design adopts a system solution combining MCU and FPGA, with AVR single-chip microcomputer ATmega128 and Altera's Cyclone series EP1C3T100 as the core, giving full play to their respective advantages, such as the advanced RISC structure and powerful computing and control functions of AVR single-chip microcomputer, and the fast computing speed, rich resources and easy programming characteristics of Altera's FPGA. With reasonable design, the phase meter of this solution has the advantages of fast speed, stable and reliable, high precision, and easy to achieve "intelligence" and "automation".

1 System solution design
1.1 Comparison and selection of measurement methods
There are currently two main methods for phase measurement:
1) DFT phase measurement method is to convert the signal to be measured through A/D conversion to obtain f(n), f(n) according to discrete Fourier transform to obtain discrete spectrum F(k), f(n) and F(k) are Fourier transform pairs, and the fundamental phase of the two signals is obtained through calculation, so as to calculate the phase difference. The accuracy of DFT phase measurement is limited by the sampling accuracy of ADC. It requires high-speed ADC to oversample the signal. The measurement scheme is complicated. It can be realized as a virtual instrument on the computer through an acquisition card, so it is mainly used in occasions with high accuracy requirements and virtual instruments.
2) Filling counting phase measurement method, that is, two sinusoidal signals of the same frequency are passed through the signal shaping circuit to obtain a square wave signal. After the square wave signal passes through the phase detector, the phase difference signal of the two input signals is obtained. The sampling pulses of a fixed frequency are filled and counted to calculate the phase difference. The filling counting phase measurement method is mainly used in occasions that require a certain accuracy, the measurement frequency is not too high, but the real-time requirements are very strong. It is easy to realize digitization and automation. Low-frequency digital phase meters are suitable for the filling counting method.
The basic algorithm of the filling counting phase measurement method: If the frequency of the square wave signal after sine wave shaping is f, the period is T, the sampling pulse period is TC, and the sampling pulse counts in one period of the square wave are n, then the measured signal frequency f=1/T=1/nTC. The same method measures the time difference between the starting points of two sinusoidal waves with the same frequency as △t, and the phase difference of the two signals is △θ=△t·360°／T.
1.2 Determination of the system solution
From the system measurement method, it can be seen that data needs to be collected, calculated and displayed. Considering the advantages of Field Programmable Gate Array (FPGA), such as high integration, rich I/O resources, stability and reliability, large selection, few peripheral components, and price reduction in recent years, as well as the good human-machine interface and calculation control functions of MCU, this system is composed of MCU and FPGA to form the measurement and control body. FPGA is responsible for collecting pulse signals for frequency measurement and phase difference measurement, and MCU is responsible for reading the data collected by FPGA, calculating the frequency and phase difference of the signal to be measured and displaying them on LCD.
Therefore, the system consists of 4 parts: signal conditioning circuit to be measured, FPGA data acquisition circuit, MCU data calculation control circuit and LCD data display circuit, as shown in Figure 1.

2 Analysis and elimination of measurement errors
The perfect design of the phase measuring instrument requires not only appropriate measurement methods and system implementation solutions, but also the analysis of the causes of errors and the determination of elimination methods.
1) The influence and determination of the filling clock frequency (i.e., data sampling signal) The frequency measurement range of this phase measuring instrument is 20 Hz to 20 kHz, the range of phase difference is △θ=0° to 359.9°, the display resolution of phase difference is 0.1°, and the absolute error of the measured phase is required to be ≤2.
The measured frequency is 20 Hz≤f≤20 kHz, then the period is 50μs≤T≤50 ms.
T=50 μs, and the absolute error is 0.1°～2°.
Then the filling clock signal period is: 0.1°x50 μs／360°≤TC≤2°x50 μs／360°, that is: 1／72(μs)≤TC≤1／3.6(μs), and the filling clock frequency can be obtained:
3.6 MHz≤fC≤72 MHz.
Within T=50ms, the filling pulses of TC=1/3.6(μs) are counted, and the count value Nmin=180000≤218; the filling pulses of TC=1/72(μs) are counted, and the count value Nmax=3600000≤222.
This design takes into account the convenience of MCU calculation and frequency division to obtain signals. The filling clock signal frequency fC=20 MHz, the absolute measurement error <1°, and the FPGA counts the time difference corresponding to the period and phase of the signal to be measured under the action of the 20 MHz clock signal. The binary data bits sampled by the FPGA are 20 bits, which can ensure the measurement accuracy.
2) The influence and elimination of zero drift in the signal conditioning circuit to be measured The main function of the signal conditioning circuit to be measured is to shape the input signal into a rectangular wave, usually using a zero-crossing comparator or a Schmitt trigger.
The zero-crossing comparator may oscillate near the zero potential. When the input signal is near the zero potential, the voltage comparator is in the amplification area, and the shaped rectangular wave will jitter at the edge, making the system unable to measure. To eliminate this jitter, a Schmitt trigger can be used. In order to ensure the accuracy of the measurement, the Schmitt trigger must meet two conditions: first, the amplitudes of the two measured signals are basically equal, and second, the threshold levels are basically close.
3) The influence and elimination of the steepness of the edge of the wave after shaping If the rectangular pulse signal output after shaping is directly sent to the FPGA, the FPGA cannot immediately obtain a stable digital pulse signal, which will greatly affect the accuracy of the system. This is mainly caused by the fact that the edge of the square wave after shaping is not steep enough. To solve this problem, one is to select a device with a large slew rate, and the other is to add a differential circuit at the back end of the comparator to enhance the edge of the pulse signal.
4) The influence and elimination of the accuracy of medium and low frequency measurements A 20 MHz data sampling signal is used to cyclically count the time difference corresponding to the period and phase difference of the measured signal, with an accuracy of 0.05 μs, and the unit of the 20-bit digital quantity is 0.05 μs. The measured signal is used to refresh the sampling count, and high-frequency multiple measurements and low-frequency measurements are achieved. The time count is accurate and reliable, so that the FPGA can provide stable data for the MCU.

3 Design of system hardware circuit
3.1 Design of front-end signal conditioning circuit
Although the Schmitt trigger (hysteresis comparator) can effectively eliminate the jitter caused by the zero crossing of the comparator, there is a phase difference between its output signal and input signal. If the amplitudes of the two measured signals are basically equal and the threshold levels of the two Schmitt triggers are very close, the phase error introduced by the Schmitt trigger has almost no effect on the measurement system error.
The LM339 has four independent voltage comparators. The characteristics of this voltage comparator are: small offset voltage, typical value is 2 mV; wide power supply voltage range, dual power supply voltage is ±1～±18 V; wide internal resistance limit for comparison signal source. The difference between the in-phase and inverting input voltages greater than 10 mV can ensure that the output can be reliably converted from one state to another. The output end is equivalent to a crystal triode without a collector resistor. When in use, a resistor is generally connected from the output end to the positive power supply. If the interference near the jump voltage value does not exceed the hysteresis AU, the output voltage value will be stable. Positive feedback can speed up the response speed of the comparator. Since the positive feedback added by the hysteresis comparator is very strong, much stronger than the parasitic coupling in the circuit, the self-oscillation caused by the parasitic coupling of the circuit can be avoided. By adjusting the potentiometer, the threshold levels of the two Schmitt triggers are basically equal, ensuring that the input circuit does not bring errors to the phase difference measurement. The circuit is shown in Figure 2.

3.2 System measurement circuit design
The phase meter is designed with the microcontroller as the core. If its crystal oscillator is 24 MHz and the counting error of the microcontroller C/T is ±0.5 μs for one machine cycle, the absolute error is 360°x0.5 μs/50μs=3.6°. Therefore, it is difficult to meet the measurement requirements when the frequency
of the measured signal is very high. This design adopts a solution combining AVR microcontroller and FPGA. FPGA realizes data acquisition and converts the time difference corresponding to the frequency and phase difference of the measured signal into binary data and transmits it to the microcontroller; the microcontroller obtains data from the FPGA and displays the frequency and phase difference of the measured signal on the LCD after data processing such as calculation and conversion. The
system electrical schematic is shown in Figure 3. The MCU adopts AVR microcontroller ATmega128 from ATMEL, which has an advanced RISC structure. Most instructions are completed within one clock cycle. There are 32 8-bit general working registers and peripheral control registers, which overcomes the bottleneck brought by the single accumulator data processing of general microcontrollers. It has 128 KB of in-system programmable Flash, 4 KB of EEPROM and 4 KB of internal SRAM, and follows the boundary scan function of the JTAG standard. It supports extended on-chip debugging and can program the Flash, EEPROM, fuse bits and lock bits through the JTAG interface.

The FPGA uses the Altem Cyclone series EP1C3T100, the configuration chip is EPCS1, the VHDL function program will generate .sof and .pof files after full compilation, the configuration download is Byte-Blaster II, [Mode] item selects "JTAG" to configure the .sof file into the FPGA chip EP1C3T100 for debugging; [Mode] item selects "Active Serial Programming" to download the .pof file into the configuration chip EPCS1, and the system runs normally when it is powered on again.
The LCD uses HTM12864, which is a 128x64 serial data transmission liquid crystal display, and the backlight is controlled by an optocoupler.
ATmega128 and EP1C3T100 design their own JTAG interfaces. Figure 3 shows the interfaces D0~D19, EN, Dsel, LCN between ATmega128 and EP1C3T100; RET, D/C, SCLK, DATA between ATmega128 and HTM12864; the input signals FAin and FBin of EP1C3T100, 66 MHz external active crystal oscillator, and configuration chip EPCS1.

4 System Software Design
4.1 FPGA Data Acquisition VHDL Program Design
The VHDL program design of FPGA data acquisition is completed on the Altera QuartuslI development software platform and experimental development system. The program design adopts the top-to-down design method. The module structure of the FPGA system is shown in Figure 4. The sampling signal generation module completes the frequency division of the clock signal source and obtains CLK=20 MHz; the signal sampling module to be measured outputs the period and phase difference data of the signal to be measured under the action of the period gate signal Tk and the time reset signal Tcr of the control signal generation module; the measurement data extraction module outputs the period and phase difference data respectively under the action of the phase detection signal JXc and the count extraction signal Lad, and under the control of the output enable signal EN and the data type signal Dsel, and is handed over to the MCU for processing and display.

Under the control of the single-chip microcomputer output enable signal EN and the data type signal Dsel, the FPGA outputs the binary data simulation waveform corresponding to the frequency and phase difference of the measured signal as shown in Figure 5. The VHDL program is compiled and debugged to generate a .pof file and downloaded to the configuration chip EPCS1 to implement the designed function.

4.2 Design of ATmega128 operation control program
AVR single-chip microcomputer ATmega128 reads the 20-bit digital quantity of frequency and phase difference from FPGA. Since FPGA counts the time difference corresponding to the period of the signal to be measured and the phase difference of two signals with the same frequency under the action of 20 MHz data acquisition signal, the unit of 20-bit digital quantity is 0.05μs. The single-chip microcomputer calculates these digital quantities to obtain the frequency and phase difference of the signal to be measured.
Design idea of ​​single-chip microcomputer operation control program: The single-chip microcomputer (ATmega128) reads the period of the signal to be measured and the time difference corresponding to the phase difference of the two signals to be measured from FPGA (EP1C3T100) through control signals EN and Dsel, calculates and converts the read data, and sends it to the LCD display to display the frequency, phase difference and related information of the signal to be measured. The main program flow chart is shown in Figure 6. The source program consists of the main program and several subroutines. The main program is a loop execution program.

1) MCU reads data from FPGA
According to the 20-bit digital interface between MCU and FPGA, data is read from PA, PB and PC (lower 4 bits) of the MCU and combined into 20-bit data. The control lines EN and Dsel control the FPGA to release data. When Dad=1, FPGA transmits the phase difference data of the signal to be measured to the MCU; when Dsel=0, FPGA transmits the period data of the signal to be measured to the MCU; when EN=1, FPGA releases data to the MCU, and when EN=0, FPGA prohibits releasing data to the MCU.
2) Calculation of frequency and phase difference data
In order to achieve the required accuracy of measurement, data cannot be lost during calculation, so the method of expanding multiple fixed-point data acquisition is adopted to ensure accurate data calculation. Calculation is performed according to the following method: signal frequency F=106/T, the calculation result is accurate to 1 Hz; phase difference △θ=△tx360°x10/T, the calculation result is accurate to 0.1°.
3) LCD display shows frequency, phase difference and other related information
This design uses HTM12864 (128x64) LCD display, the controller is S6B0724, and the data and control interface with the microcontroller is: CS, RET, D/C, SCLK, DATA. The backlight is controlled according to the key action, and the key is used to switch the display information.

5 Conclusion
This design adopts the method of combining MCU and FPGA. The ATmega128 microcontroller has advanced RISC structure and operation control function, while the FPGA has high integration and high-frequency data acquisition function. They play their respective advantages. Both have JTAG interface online debugging and programming functions. The digital phase meter designed by this method has high accuracy, stability and reliability. This instrument measures the frequency of the sine signal and the phase difference of two sine signals of the same frequency, which better meets the technical index requirements of the design.