8b/10b SERDES interface design based on Jingwei Yager low-power FPGA

This solution uses CME's latest low-power series FPGA HR03 as the platform to implement 8/10b SerDes interface, including SERDES transceiver unit, and realizes SERDES CDR (Clock Data Recovery) through a fully digital method to complete 100~200Mhz inter-board SERDES single-channel communication. This SERDES interface solution has the characteristics of low cost, high flexibility and short R&D cycle.

1Hardware interface:

The hardware interface is shown in the figure, which mainly includes sending and receiving modules.

The transmitting module includes an 8b/10b encoder, a serial-to-serial converter, a phase-locked loop (PLL) frequency synthesizer and a transmitter, and the receiving module includes an 8b/10b decoder, a comma detector, a serial-to-parallel converter, a clock data recovery (CDR) and a receiver.

The 8b/10b encoder is used to map the byte signal sent from the upper layer protocol chip into a DC balanced 10-bit 8b/10b code. The parallel-to-serial conversion is used to serialize the 10-bit encoding result. The high-speed, low-jitter clock required for the parallel-to-serial conversion is provided by the phase-locked loop. The transmitter is used to convert the high-speed serial code stream at the CMOS level into a differential signal with strong noise resistance, and send it to the receiver via the backplane connection or optical fiber channel.

At the receiving end, the receiver restores the received low-swing differential signal to a CMOS-level serial signal. The CDR extracts the clock information from the serial signal to complete the optimal sampling of the serial data. The serial-to-parallel conversion uses the clock recovered by the CDR to convert the serial signal into 10-bit parallel data. The comma detector detects special comma characters and adjusts the word boundary. The parallel data with correct word boundary is decoded by 8b/10b, restored to a byte signal, and transmitted to the upper-layer protocol chip to complete the entire information transmission process.

In the actual design, the CDR part is completed by pure logic circuits and is the core part of the design. The implementation scheme of digital CDR in HR03 will be introduced below.

2-Digital CDR:

The CDR module recovers the embedded clock from the data, and then the receiver performs data bit alignment according to the recovered clock and word alignment through comma. Finally, the data is decoded into 8b/10b for system use.

This solution adopts the same frequency multi-phase clock sampling method. The specific implementation process uses PLL to generate 4 clocks with the same clock frequency and a phase difference of 90 degrees, namely clk0, clk90, clk180, and clk270. These four clock outputs are completely synchronized. The data is sampled using 4 clocks to obtain a 4x oversampling effect. The specific implementation process is shown in the figure below:

During data clock recovery, the incoming data is input into four flip-flops respectively and sampled using four different phases. Care should be taken to ensure that the delay from the input pin to the four flip-flops is basically consistent.

The trigger of the first column of triggers is triggered by the rising edge of the clock CLK0, CLK90, CLK180, and CLK270 respectively. In this way, four data sampling points can be obtained. In this way, the original clock cycle is divided into four separate 90-degree areas. If the system clock is 200MHz, the circuit shown in the figure above is equivalent to generating a sampling rate of 800MHz.

The output sampled data has metastability problem only through the first-order trigger, so the sampling point needs to be further processed. Here, the four sampling points can be further triggered to eliminate the metastability problem, so that the sampling point can be moved to the next same clock domain. Usually, the removal of metastability needs to go through two or three levels of processing, which makes there will be invalid data before the valid data is output. In the first stage of data sampling, the circuit detects the transmission of data on the data line. When data transmission is detected, the validity of the transmitted data is confirmed. After confirming that the data is valid, a high level is output to indicate that data is transmitted at the sampling point.

Because there are four outputs in the end, a multiplexer is needed to select the data. The correspondence between the transmitted data and the sampling clock is shown in the figure above. The correspondence is divided into four cases, each of which corresponds to an optimal sampling clock. The system determines which clock is the best sampling clock by judging the data edge position information, and uses the multiplexer to select the data bit from the selected clock domain. For example, if the detection circuit determines that the data sampled from clock domain A is valid, the data sampled in clock domain A will be output through the output terminal.

3 Conclusion:

Through the CDR circuit of pure digital circuit, without the support of hard core, the interface design of SERDES on FPGA was completed, and through experimental transmission test, 100~200Mbps data transmission can be completed on HR03 FPGA.