A complete solution for low-cost digital chip automatic tester based on FPGA

Project background and feasibility analysis

Project name: Research and development of low-cost digital chip automatic tester based on FPGA

Research purpose: To use the VertexⅡ Pro development board system to implement functional testing of Flash memory.

Research Background:

With the increasing complexity of circuits and the decreasing size, testing has become an urgent problem that needs to be solved. Especially since entering the development stage of deep submicron and advanced synthesis, the functions of system-on-chip (SoC) have become more powerful by integrating various IP cores, but it has also brought a series of design and testing problems.

Testing is the most expensive and difficult part of VLSI design. This is mainly due to the following reasons:

1. Currently, IC testing is done through ATE (Automatic Tester) testing platforms. Since ATE is expensive (usually several million dollars per unit), the testing cost has always been high, which is the main reason for the high testing cost.

2. As the clock frequency of VLSI devices increases exponentially, the cost of high-frequency and high-speed testing also increases accordingly.

3. The increasing integration of transistors in VLSI devices makes the internal modules of the chip more difficult to test and the complexity of testing increases, which in turn increases the cost of testing.

This study hopes to use FPGA to partially implement the test function of ATE, which can significantly reduce the test cost to a certain extent while meeting the test requirements.

Features:

Complete test structure and relatively comprehensive test functions.

Using March C's optimization algorithm, the test time is shorter.

Able to cover most of the Flash memory faults.

Research innovations:

1. Low cost and high cost performance;

2. With open architecture;

3. Small size and portable.

Project Implementation Plan

1 Flash memory failure type:

1) Stuck-at Fault (SAF Fault): A functional fault in which a storage unit constantly stores 1 or 0.

< 2) Transition fault: The storage unit cannot transition from the 0 state to the 1 state (↑) or cannot transition from the 1 state to the 0 state (↓).

3) Coupling fault (CF fault): A fault in which the value of a storage unit may change due to the change of the state of other storage units. The causes of its formation include short circuit or parasitic effect.

There are three forms of coupling faults: phase reversal, same potential, and bridge/state.

Inversion (CFins): The phenomenon in which the change of state of one storage cell causes the value of other cells to become opposite.

CFids: The phenomenon that the state change of a storage cell causes the value of other cells to be a specific logical value (0 or 1).

Bridge and State (SCF): The phenomenon where a certain state of one storage unit causes another storage unit to be in a specific state.

4) Data Retention Failure (DRF): A failure in which a memory cell cannot maintain its logic value after a period of time. This failure is generally caused by the disconnection of the pull-up resistor.

The above four fault models are possible failure models of all memories.

In addition, Flash has the following failure modes: 5) Gate Program Disturb (GPD) and Gate Erase Disturb (GED): Programming or erasing a memory cell causes erroneous programming or erasing of other cells on the same word line.

6) Drain Program Disturb (DPD) and Drain Erase Disturb (DED): A program or erase operation on one memory cell causes an erroneous program or erase operation on another cell on the same bit line.

7) Over-erase (OE): Over-erasing the memory will cause the next programming of the memory cell to be ineffective, thereby failing to obtain the correct operation result.

8) Read Disturb (RD): A read operation on a memory cell causes erroneous programming of the cell.

The above faults are all array faults, and there are also peripheral circuit faults.

9) Address decoding failure (ADF); a specific address cannot access the corresponding storage unit, or multiple units are accessed at the same time, or a specific storage unit can be accessed by multiple addresses.

2 March C algorithm:

< Based on the fault models of the Flash memory listed above, it is necessary to select a test algorithm with high coverage and high efficiency to test and verify it.

This study uses the March C algorithm to achieve this. It is expressed as:

{↓↑(w0);↑(r0,w1,);↑(r1,w0);

↓(r0,w1); ↓(r1,w0); ↓↑(w0)}

The symbols have the following meanings:

↑ indicates address ascending order

↓ indicates address descending order

↓↑ means the address can be in ascending or descending order

w0 write 0 operation

w1 write 1 operation

r0 read 0 operation, the expected value is 0

r1 read 1 operation, the expected value is 1

The running time of the March C algorithm is 10N, where N represents the storage capacity of the memory.

Its fault coverage can reach over 90%.

In addition, the March algorithm will be optimized during the research process.

3 Hardware Circuit

2. Required development platform

Because PowerPC is needed for processing, we choose the advanced board - Virtex-2 Pro (built-in 2 PowerPC, SDRAM, Ethernet, CF, SATA, audio Codec)

Basic functions required: internal PowerPC processor, SRAM Flash, USB1.1/2.0, RS-232, LCD display

Other resources needed

1.FPGA and DUT interface, DUT module design

2. Test equipment

PC, multimeter, oscilloscope, etc.

3. Policy and development tools

ISE、EDK、CAD etc.