Design of control circuit of all-optical current transformer based on FPGA

　　As the main equipment for high-voltage power grid detection, current transformers not only provide parameters for electric energy measurement, but also provide the basis for relay protection. With the development of the national smart grid and ultra-high voltage power grid, traditional electromagnetic current transformers have gradually exposed their fatal defects, such as extremely difficult insulation at high voltage levels, easy magnetic saturation at higher voltages, resulting in reduced measurement accuracy, etc. In contrast, fiber-optic current transformers have many advantages such as strong anti-electromagnetic interference ability, reliable insulation, high measurement accuracy, simple structure and compact size, and are currently a hot research topic. As the core component of fiber-optic current transformers, their detection and control circuits have a very important impact on the current detection accuracy and range.

　　At present, there are two main schemes for the detection and control circuit. One is to use digital signal processing chip (DSP) as the core. As the speed of DSP is getting faster and faster, DSP has become the first choice for many data processing and signal detection schemes, but it is its bottleneck in timing control. Since the timing control accuracy and speed directly affect the detection accuracy of the optical fiber current transformer, the control accuracy of this scheme is limited; the other is to use field programmable gate array (FPGA) and DSP as core devices, combining the advantages of both, using FPGA to complete system timing control, and DSP to implement various digital signal processing algorithms. Although very high control accuracy can be obtained, the system structure is relatively complex and the reliability is reduced. With the development of FPGA technology, FPGA is not only used for precise timing control, but also can realize complex digital signal processing functions. This paper uses FPGA to realize precise timing control while realizing very complex signal processing algorithms, and uses FPGA as the core device to complete the design of optical fiber current transformer signal detection and control circuit, and uses this circuit to control the optical fiber current transformer sensor head for current testing and calibration. The experimental results show that the system control accuracy meets the requirements of 0.2 S-level measurement accuracy.

　　1 Signal detection and control principle of all-optical current transformer

　　All-fiber current sensing technology uses the Faraday effect to detect current. When a beam of linearly polarized light passes through a material in a magnetic field, the vibration plane of the polarized light will rotate to a certain extent. The information of the magnetic field and the current that generates the magnetic field can be obtained by measuring the rotation angle. The rotation angle of the vibration plane can be obtained by formula (1):

　　Where: Φ is the magnetic Faraday deflection angle; V is the Verdet constant of the optical fiber; H is the magnetic field intensity; l is the distance of interaction between light and magnetic field.

　　The essence of the Faraday effect is magneto-induced circular birefringence, which can be explained as follows: linearly polarized light can be decomposed into two beams of circularly polarized light with opposite rotation directions (left-handed and right-handed). The external magnetic field causes the refractive index of the material to be different for these two beams of orthogonal circularly polarized light, resulting in their propagation speeds in the material being no longer consistent. After propagating for a certain distance, the two beams of circularly polarized light will produce a certain phase difference △Φs, causing the polarization plane of the corresponding linearly polarized light to rotate. By measuring this phase difference, the magnetic field and the current information that generates the magnetic field can be obtained. At the same time, it has been proved that the relationship between the phase difference △Φs and the Faraday rotation angle Φ is △Φs=2Φ.

　　If the optical path is closed around the current-carrying conductor, and when the magnetic field H is generated only by the current in the conductor passing through the sensing fiber loop, equation (1) and Ampere's loop law can be used to obtain:

　　△Φs=2VNnI (2)

　　Where: △Φs is the magneto-Faraday phase difference; V is the Verdet constant of the optical fiber; N is the number of times the light beam surrounds the conductor; n is the number of conductors in the sensing optical fiber loop; I is the current passing through a single conductor.

　　It can be seen that the phase difference between two orthogonal circularly polarized light beams after the Faraday effect is proportional to the number of times the light beams circle the conductor and the total current passing through the sensing fiber loop. Since the number of times the light beams circle the conductor is known, the magnitude of the current to be measured can be calculated as long as △Φs is measured.

　　2 Signal detection and control circuit implementation

　　The overall block diagram of the signal detection and control circuit is shown in Figure 1. The optical fiber sensor head inputs the optical signal carrying phase difference information into the photodetector (the phase difference is proportional to the amplitude of the photodetector output signal). The voltage signal output by the photodetector is firstly DC-isolated, then amplified and filtered, and converted into a digital signal by the A/D (analog-to-digital converter), and then sent to the digital signal processing unit based on FPGA. Data demodulation, integration and filtering are performed in the FPGA, and the step height of the step wave is calculated by the step wave generation algorithm. After that, the step wave is superimposed with the fixed period modulated square wave under the control of the timing control unit, and then converted by the D/A (digital-to-analog converter) controlled by the FPGA to form an analog voltage waveform, which drives the phase modulator, thus completing a closed-loop feedback of the system. In addition, the step height data of the step wave is transmitted to the control computer by the asynchronous serial transceiver (UART) after digital filtering. Since the step height of the step is related to the magnitude of the current to be measured, the upper-level software can obtain the magnitude of the measured current through simple processing. The timing control of the entire system is completed in the FPGA, and the timing control of square wave modulation, A/D acquisition, digital step wave feedback, data output, etc. is required to have a strict synchronization relationship.

　　Figure 1 Block diagram of signal detection and control circuit

　　2.1 Preamplifier and filter circuit

　　Since the output signal of the photodetector is relatively weak and contains high-frequency noise information, it needs to be amplified and filtered before the subsequent A/D conversion and quantization into a digital signal. Therefore, the amplification and noise suppression capabilities of the preamplifier and filter circuits for useful signals will affect the subsequent measurement accuracy. The preamplifier circuit uses the differential op amp AD8130, which has a very high common-mode rejection ratio and is particularly suitable for applications that require low noise, low harmonic distortion and high common-mode rejection ratio in weak signal amplification. The frequency of the effective AC square wave signal output by the photodetector is about 200 kHz. In order to ensure that the square wave signal passes through the back-end filtering circuit without distortion, the high-frequency cutoff frequency of the filtering circuit must be designed without losing 20 times the harmonics of the square wave base frequency signal. At the same time, in order to avoid high-frequency noise from entering the back-end sampling and quantization module, the high-frequency cutoff bandwidth cannot be too wide. In this design, a π-type filter with a bandwidth of 4 MHz is used to achieve front-end filtering.

　　2.2 Data Acquisition Circuit

　　To ensure the measurement accuracy of 0.2S level (i.e. 0.2000), the A/D conversion bit number needs to reach more than 10 bits. In addition, in order to ensure the number of high and low level sampling times of each cycle of the 200 kHz square wave signal, so as to improve the sampling accuracy by accumulating and averaging, it is necessary to sample the high and low levels of the square wave more than 20 times in each cycle and then average them, which requires the analog-to-digital converter sampling rate to be greater than 8 MS/s. A certain margin is reserved in the design, and the analog-to-digital converter AD9248 with a quantization bit number of 14 bits and a sampling rate of 20 MS/s is used. The chip adopts a multi-stage differential pipeline structure with output error correction logic, integrates two high-performance sampling and holding amplifiers and a reference voltage source, and only needs to provide a control clock. Its conversion data automatically appears at the data port after 7 clocks, which is very convenient for precise timing control occasions.

　　2.3 FPGA Control Circuit

　　FPGA is the core of the optical fiber current transformer control circuit to realize signal detection and closed-loop control. As shown in Figure 1, its main functions are to generate the control timing of the entire control system; complete A/D acquisition control and data reading and storage; process the collected digital signals according to the predetermined demodulation and integration algorithm, and send the processed data to the step wave generation algorithm at the same time, and transmit it to the UART serial port control module after filtering to complete the data communication with the computer; in addition, the data generated by the step wave generation algorithm is superimposed with the square wave data to control the D/A converter to output the corresponding analog signal. FPGA control timing is shown in Figure 2. After the circuit is powered on and reset, the FPGA program is loaded and the peripheral A/D, D/A and other program-controlled circuits and interfaces are initialized; the FPGA internal timing control module generates a modulated square wave with a period of 5 μs, which is output to the D/A through the D/A control interface to generate an analog square wave signal with the same period and control the back-end optical modulator to generate a phase shift of ±π/2, ensuring that the phase detection sensitivity of the front-end optical fiber sensing part is the highest; the front-end input signal of the analog-to-digital converter is an AC signal containing phase difference information. The difference between the high and low levels of the signal is proportional to the phase difference. By detecting the difference between the high and low levels of the signal, the current phase difference can be indirectly obtained, thereby obtaining the corresponding current size according to the aforementioned theory. The signal period is consistent with the square wave period.

　　FPGA controls the A/D converter through the timing control unit to sample the high level and low level of the signal multiple times in each square wave cycle, average and subtract, and obtain the demodulation information of the signal, that is, the phase information. Since the phase difference of the front-end optical fiber sensing part is 0, it indicates that a closed-loop control is achieved. Therefore, the demodulated phase information needs to be converted into step wave step data through the step wave generation algorithm, and then the step data and the square wave data are accumulated and output to the D/A converter through the back-end 200 kHz fixed square wave and digital step wave superposition generation module. The D/A converter outputs an analog signal to drive the control phase modulator to generate the phase difference information to offset the detected phase difference information, forming a closed-loop control. The step wave accumulation judgment program should be designed in this design. When the step wave accumulation data value exceeds the 2π phase shift generated by the driving phase modulator, it should be subtracted from the corresponding value of the 2π phase shift generated by the phase modulator before accumulation. Since the height of the step wave reflects the phase difference caused by the measured current, this value is also linearly related to the measured current. After digital smoothing filtering, this value can be transmitted to the upper control interface through the UART communication interface designed inside the FPGA for calculating the current measured current.

　　Figure 2 FPGA closed-loop control timing diagram

　　2.4 Digital-to-analog conversion and drive circuit

　　The function of this part is to convert the digital signal output by the 200 kHz fixed square wave and digital step wave superposition generation module into an analog voltage signal, and then control the phase modulator through amplification and amplitude adjustment of the power drive part (when the D/A is at full scale, the analog voltage value generated is twice the half-wave voltage of the phase controller), thereby generating an additional feedback phase shift in the optical fiber sensing loop to offset the phase difference detected in this closed-loop control cycle. The selection of D/A mainly considers the analog signal output settling time, gain error, output linearity and resolution. The D/A output signal settling time not only has an important influence on the closed-loop control bandwidth, but also has a great influence on the leading and trailing edges of the output step wave when its settling time is long, resulting in the elongation of the spike pulse of the input signal at the front end of the analog-to-digital converter, and the effective sampling time window becomes shorter, so the shorter the settling time, the better. The gain error and output linearity of the D/A determine the error and linearity of the output analog signal, and the error and linearity of the analog signal are applied to the phase modulator or directly affect the control error of the feedback phase, so it is necessary to select an analog-to-digital converter with small gain error and output linearity. The resolution of D/A directly determines the minimum resolution accuracy of phase control, and its resolution is better than that of A/D. The design uses a 16-bit high-speed D/A chip AD9726 to implement the analog-to-digital conversion function. Since the chip has a current output, the back end uses a high-speed operational amplifier AD811 to realize the current output to voltage output and voltage amplitude amplification function.

　　3 Experimental verification and discussion

　　In order to verify the performance of the above control circuit, an all-fiber current transformer device was built in combination with the front-end fiber current sensor head module. At the same time, a large current generator (AC, effective value 0 ~ 5000A, 50 Hz) was used as the test current source, and a 0.01-level (error less than 0.01%) standard current transformer was used as the benchmark. According to the national standard requirements, a set of accuracy calibration system was built to calibrate the measurement accuracy of the all-fiber current transformer, thereby verifying the indicators and functions of the above control circuit. Figure 3 is a screenshot of the 50 Hz AC signal obtained by the upper control interface through the serial port. It can be seen that the period and amplitude information of the 50 Hz AC signal can be effectively demodulated through the above control circuit, thereby realizing the closed-loop control function of the fiber optic sensor head.

　　Figure 3 50 Hz AC signal obtained by the upper control interface

　　The rated primary current value Ipr of the prototype of the all-optical current transformer device built on the basis of this control circuit is set to 100A-4000A. According to the national standard requirements, within the range of 1%-120% of Ipr, the measurement error of the measured current value imeasured is shown in Table 1, where the standard current value istandard refers to the current value (effective value, the error between the true value and the actual value is less than 0.01%) obtained by detecting the measured current by a 0.01-level standard current transformer, and the unit is A; the digital output of the demodulated signal of the prototype refers to the digital quantity output by the prototype after demodulating the measured current; the current value isolation demodulated by the prototype refers to the value obtained by multiplying the digital output of the demodulated signal of the prototype by a fixed transformation ratio, which represents the current value (effective value) of the demodulated output, and the unit is A; the current error is the error between istandard and isolation.

　　Figure 4 Measured error curve of full range

　　According to the data in Table 1, the error curve within the full range can be obtained, as shown in Figure 4. It can be seen intuitively that the measured errors within the full range meet the requirements of 0.2 S-level measurement accuracy. That is, the designed circuit completes the closed-loop control of the optical fiber sensor head and the demodulation of the test data.

　　This paper preliminarily studies the closed-loop detection control circuit for all-fiber current transformers. Based on a single-chip FPGA, signal acquisition, data output, and computer communication control and data demodulation, integral filtering, step wave generation and other algorithms are implemented to complete the detection and closed-loop control of the output signal of the fiber-optic current transformer sensor head. The control circuit has the characteristics of simple structure, high integration, fast closed-loop control speed, and high control accuracy, laying a foundation for the development of all-fiber current transformers that meet the testing needs of power grids. In addition, the all-fiber current transformer prototype developed based on the control circuit has achieved a 0.2 S-level measurement accuracy in the rated primary current range of 100 A~4000 A after testing, which preliminarily meets the requirements of the power grid for the measurement accuracy of current transformers.