PTC/ESD solution based on USB3.0 circuit reliability

USB 3.0 has a transmission rate of up to 5Gbit/s, and the power bus has a maximum output current of up to 900 mA. Therefore, it is extremely important to prevent electrical transients and overcurrent faults in the circuit. Designers must carefully select appropriate thermistors (PTC) and electrostatic discharge (ESD) solutions to ensure signal integrity and reduce the risk of system failure.

Since the Universal Serial Bus (USB) specification was released in 1996, more than 3.5 billion USB connection devices for computer peripherals have been shipped as of 2012. In 2010, when the first batch of devices supporting the USB 3.0 specification were launched, sales reached about one million units, and in 2012 it increased to about five million units, which shows that its market growth is quite rapid.

Compared to USB 2.0, USB 3.0 has four additional data channels with a transfer rate of up to 5 Gbit/s (Figure 1), and the power bus has a maximum output current of up to 900 milliamperes (mA). These new specifications, coupled with the continuous reduction in chip size, make the problem of preventing circuit electrical transients and overcurrent faults more important and complex, because at high-speed transmission, even a small electrostatic discharge (ESD) and short circuit accident will cause serious damage to the system.


图1 USB 3.0增加双差分数据对，藉以达成5Gbit/s高速传输速率

由于晶片灵敏度、讯号完整性和系统可靠性都是系统设计人员非常关注的事情，因此USB 3.0系统上的寄生电容、低箝位电压和低电阻都成为电路保护元件选择的关键指标。由于USB 3.0电源线可允许更大电流通过，电流保护器可有较低的电阻，在确保低压降方面也变得至关重要。一项成功设计的关键是要掌握保护技术，如热敏电阻（PTC）、压敏电阻和ESD方案等，本文将详细解释须考虑的设计因素。

USB 3.0飙高速电路保护挑战更艰钜

USB 2.0到USB 3.0最重要的物理变化是引进SSRX+/SSRX和SSTx+/SSTx两个差分数据，并维持和现有D-/D+资料汇流排并列运行的模式，这允许资料全双工同时传输，改进USB 2.0汇流排只能单个双工传输的问题。此外，USB 3.0还将电源汇流排上的电流从500毫安培增加到900毫安培，扩增外部设备供电的选择，不再需要额外电源配套方案。

由于USB 3.0引进额外的差分数据，引发更多ESD防护需求，过去以分离元件保护每个单独资料线的方式已不足以保护其电路，工程师面临的挑战是要找到更好的ESD和电压瞬态保护方案，使敏感性资料线在没有增加讯号畸变电容的情况下也能得以保护。现阶段，业界大多采直接放在资料对中的新半导体阵列ESD保护装置，同时保护传统USB 2.0资料线，以及USB 3.0额外的资料线。

与此同时，USB 3.0规范第11.4.1.1.1中规定，为安全起见，主机和所有自供电集线器须实现过电流保护，该集线器须检测过电流情况，并将其报告至USB控制软体。过电流限制机制须在毋须用户干预的前提下自行复位，聚合物PTC和固态开关就可用于过电流限制的方法之一。

根据UL60950-1标准要求，USB 3.0可能还需要其他过电流保护功能，USB汇流排收发器晶片或电源管理晶片虽已提供部分电流限制功能，但是当晶片不包含电流限制或附加保护功能时，电路设计人员须为电源汇流排设计电流限制PTC.

在电源汇流排上安装聚合物PTC可在短路的情况下限制电流，并防止由突然的短路引起的过电流损坏，还可帮助实现UL60950-1标准中第2.5节（有限电源，表2B）的规定，限制短路电流在5秒内小于8安培。

相关的USB集线器应用程式和USB 3.0的过电流保护规范如11.4.1.1.1条中陈述，如果下行埠的总电流超过预定值时，过电流保护电路可消除或减少所受影响的下行埠功率。预设值不能超过5安培，且须足够大于所允许的最大埠电流或时间延迟的瞬态电流（例如开机、动态连接或重新配置时），达成过电流保护。

肩负USB 3.0埠保护重任PTC选用规格大有学问

图2所示为用于多埠集线器配置的PTC解决方案，表1则显示推荐的单一埠和两个埠中联动的PTC元件，并针对新的USB电池充电规范1.2版列出所需的PTC方案。


Figure 2: USB 3.0 multi-port hub configuration architecture

When selecting a PTC for USB port protection, several key parameters must be considered, including the maximum current that must support 900 mA, the operating temperature of the PTC location, the trigger speed, and the DC resistance. All PTCs in Table 1 can protect USB 3.0 ports with a maximum current of 900 mA and will not trip even if the maximum operating temperature reaches 60°C.

Since rapid temperature changes may reduce the trigger rate of the PTC, this is also an important aspect of the PTC selection process. Designers should consider incompatible USB 3.0 devices and loads of 900 mA when selecting PTCs, so that the PTC has a maximum available current of more than 900 mA at the maximum operating temperature. Otherwise, the PTC may trigger incorrectly.

Each PTC must also trigger a short-circuit fault at a speed of less than 5 seconds at a current of 8 amps, so it is important to comply with the UL60950-1 limited power supply specification and limit the current in the USB 3.0 specification to 5 amps. The

last key parameter for selecting the most suitable PTC is the DC resistance. Since USB 3.0 now provides a maximum current of 900 mA, the power consumption in the circuit must be further reduced. In addition, the voltage drop of the components across the power bus must also be reduced, especially when the circuit resistance budget is very tight.

Overall, the main goal of selecting a PTC is to ensure that the current device can withstand at least 900 mA at the highest temperature. For example, if 60°C is set as the worst design temperature, a single-port application should choose the smallest size and can support the maximum required current of 0.95 amps, such as the first solution in Table 1. If a PTC is used to protect two USB 3.0 ports, the third solution in Table 1 is a good choice because it can maintain a current of 2.19 amps at 60°C, meeting all safety considerations.

Enhanced USB 3.0 circuit protection external ESD components are imperative

. The additional data lines of USB 3.0 will also be subject to greater ESD threats because they provide more possible entry channels for electrical transients. Although modern chips often have a certain degree of ESD self-protection function (usually in the range of 500~2kV), it is still insufficient for USB 3.0 circuits, so additional ESD protection components must be introduced.

The level of electrostatic protection is graded according to the MIL-STD HBM model with a 1,500 ohm (Ω) discharge resistor. In the MIL-STD model, a 2kV pulse is equivalent to a 330 ohm discharge resistor and a voltage of 500 volts based on the IEC 61000-4-2 model (Figure 3). The current human body discharge model (HBM) available pulse is one-fourth of the IEC model available at the same transient voltage. When an electrostatic discharge incident occurs, the voltage is often as high as 15kV or even higher, which will cause software failure, potential damage to the circuit or catastrophic failure. Therefore, additional ESD protection is necessary to improve the survivability of modern interface ports.


图3 IEC 61000-4-2 ESD电流波形

为确定外部ESD事故预防系统，业界已开发出几个测试标准，其中，IEC 61000-4-2条款受到最广泛的认可；该标准定义ESD在不同的环境和安装条件中的测试规范，如今的USB 3.0埠在此规范下，须承受至少8kV接触放电，达到IEC 61000-4-2条款第四级的要求。

USB 3.0拥有更高的资料速率，就特别须要注意元件的电流容量以保护电路，且系统设计人员在选择ESD保护元件时也须留意许多重要参数，包括动态电阻、箝位元电压、击穿电压、寄生电容、最大ESD能力、多脉冲能力、封装形状、关断状态的阻抗或泄漏电流、设备电路配置和布局的灵活性等。

现阶段，市场上有几种不同的防静电抑制技术，例如多层陶瓷压敏电阻（MLV），聚合物ESD抑制器和半导体的ESD抑制技术，是否选择正确的元件将决定USB 3.0埠的设计可靠度。由于ESD保护元件的电容、箝位元电压和动态电阻最为重要，一些保护元件制造商已实现以最小寄生电容提高讯号完整性的产品，同时有些产品的箝位元性能也达到最大化，但代价是电容很高。

举例来说，瞬态电压抑制（TVS）二极体和二极体阵列有较低的动态电阻，提供卓越的箝位元性能，并能保持非常低寄生封装电容。图4显示矽方案的箝位元性能与MLV ESD保护技术的比较，以矽为基础的解决方案的箝位元电压更低。


图4矽电阻与压敏电阻的箝位元性能比较

TVS二极体阵列提供多通道ESD保护解决方案（图5），成为目前USB 3.0保护的最佳选择。该类元件能吸收瞬态电流，并泻放电流，同时透过雪崩或齐纳二极体箝制电压位准。如图6所示为USB 3.0静电保护方案架构图。


Figure 5 Schematic diagram of TVS diode array protecting USB 3.0 circuit


Figure 6 shows the USB 3.0 electrostatic protection solution architecture

USB 3.0 circuit protection components are also very important to maintain data integrity. Any additional capacitance can cause signal distortion and reduce signal reliability. The main method to test the effect of the parasitic capacitance of the ESD suppressor on signal integrity is to perform an eye diagram test. This test requires repeated sampling of the digital signal and displaying the eye diagram on an oscilloscope to define acceptable signal quality and compliance.