Design and simulation of sub-image extraction module of linear CCD based on FPGA

In industrial production automation systems, the use of computer vision and image processing technology to achieve product quality monitoring and control has gradually become an effective application technology. Linear array CCD image sensors are widely used in many fields such as product size measurement and classification, non-contact size measurement, barcode, morphology recognition, etc. In the image detection system, a high-speed sub-image extraction and output module should be provided. This paper uses FPGA device EP3C25F256C8 and CCD linear array image sensor RL1024P to realize the sub-image extraction and output function in the linear array CCD image detection system.

1 Design of sub-image extraction module

The function of the sub-image extraction module can be described as: using FPGA devices to implement, according to the serial input black and white image and synchronization signal, extract the sub-image of the set size in the image. Assuming that the input image size is i * j, the coordinate position of a certain pixel point is (X, Y), and the size of the sub-image to be extracted is m * n, the C code is described as: for (b = 0; b

According to the requirements of system design, the linear CCD image acquisition module outputs a row of images of 1×1024 pixels in serial mode, and the sub-image extraction module receives the image data, buffers it, and then outputs a sub-image of 16×16 pixels. The external port of the sub-image extraction module is shown in Figure 1. The main signals are: pixel synchronization clock signal CCD_CLK, pixel data CCD_DATA, and the coordinates of the current input pixel CCD_ADDR[90]; in addition, N_RST and SYS_CLK are the reset signal and processing clock signal provided by the system. Among them, the CCD_DATA pixel is valid when each rising edge of CCD_CLK appears, and the position of the pixel is the CCD_ADDR[90] value.

In order to output a sub-image in each CCD_CLK cycle, SYS_CLK should be about 10 times of CCD_CLK.

This paper adopts the "image transposition buffer" method to implement the sub-image extraction module. The "image transposition buffer" is a RAM buffer that is written (updated) by row and read by column. A 1024-unit RAM buffer is set inside the FPGA, and the bit width of each unit is 16 bits. The relationship between the linear array image and the sub-image output by the linear array CCD acquisition module is shown in Figure 2. Among them, the 0th row represents the current row of the image, the Nth row is the historical row, each row has 1024 pixels, and is output in the order of pixels from p0 to p1023. Assuming that the pixel currently input by CCD_CLK is the p16 pixel of the 0th row, the corresponding 16X16 sub-image is the shaded part in the figure.

The “Image Transpose Buffer” RAM block stores the structure of the image, as shown in Figure 3.

The RAM block has a total of 1024 units, each of which is 16 bits wide and can store the most recent 16 rows of image data. Comparing Figure 2 and Figure 3, it can be found that the address number of the RAM block is equivalent to the position of a row of pixels in the linear array CCD image, and the bits D15 to D0 of a RAM unit correspond to the most recent 16 pixels in a column, which is equivalent to transposing the linear array image and then storing it in the RAM block. When writing to the RAM buffer, since the data of the linear array CCD image is input bit by bit row by row, when each CCD_CLK clock rising edge occurs, only the bit corresponding to the current pixel in the RAM buffer needs to be updated, so logically it is written to the RAM area row by row according to the image. In the FPGA device, a state machine can be designed to implement the read and write operations of the "image transposition buffer", as shown in Figure 4.

The sub-image output by the sub-image extraction module has 256 pixels. The previous output sub-image is temporarily stored in the FPGA through registers. When a pixel in the RAM area is updated, the 16X16 sliding window is moved to the right by one column of pixels, and the data in the sliding window is used as output to obtain a new sub-image.

2 Design Simulation

In the design simulation of this article, since image file parsing and image display are used, the joint simulation realized by file reading and writing with the help of MATLAB and Modelsim software can make the simulation processing more convenient and intuitive. Among them, MATLAB is used to convert image files into input pixels and display output sub-images; Modelsim is used to simulate and verify whether the FPGA design is correct.

This paper uses MATLAB and Modelsim for joint simulation, which mainly includes the following three steps. The first step is to write an m file in MATLAB, read the bmp bitmap file and write the pixel data into the file datain.txt as the input excitation signal for ModelSim simulation. The second step is to write the Testbench test file in VHDL in ModelSim, read the datain.txt file, generate a pixel signal synchronized with CCD_CLK; write a DO file for automated simulation, and then save the sub-image data output by the simulation in the dataout.txt file. The third step is to write an m file in MATLAB, parse the dataout.txt file, and display it as a 16×16 black and white picture sequence in turn to determine whether the simulation results are correct. The input image and output sub-image sequence of this design simulation are shown in Figure 5. From the simulation results, it can be seen that the design method is correct and the simulation results meet the requirements of the design function.

3 Conclusion

When using linear array CCD image sensors for product inspection, continuous and high-speed output of sub-image sequences is an essential and important link. There are many different design methods for extracting and outputting sub-image sequences using FPGA. This paper uses the "image transposition buffer" and state machine method to implement the sub-image extraction and output functions required by the system, and uses MATLAB and ModelSim tool software to jointly simulate the design. This method has the characteristics of low FPGA resource usage, simple structure, high-speed processing, and convenience and intuitiveness, which has a good reference role for other similar FPGA design projects.