Analysis of using time-interleaved ultra-high-speed analog-to-digital converters in PCB design

Acquiring synchronously sampled analog signals at billions of times per second using time-interleaved analog-to-digital converters (ADCs) is a significant technical challenge for designers and requires sophisticated mixed-signal circuits. The fundamental goal of time-interleaving is to double the sampling frequency by adding converters without sacrificing resolution and dynamic performance.

This article discusses the main technical challenges of time-interleaved analog-to-digital converters and provides practical system design guidance, including innovative component functions and design methods that can solve these problems. The article also provides FFT results measured from a 7Gsps dual-converter chip "interleaved solution". Finally, the article describes the application support circuitry required to achieve high performance, including clock sources and driver amplifiers. The

need for higher sampling speeds continues to increase.

When and why is it more beneficial to increase the sampling frequency? This question has multiple answers. The sampling speed of the analog-to-digital converter basically directly determines the instantaneous bandwidth that can be digitized in one sampling instant. The Nyquist and Shannon sampling theorems prove that the maximum available sampling bandwidth (BW) is equivalent to half the sampling frequency Fs.

3GSPS analog-to-digital converters have achieved the acquisition of 1.5GHz analog signal spectrum in one sampling period. If the sampling rate is doubled, the Nyquist bandwidth is also doubled to 3GHz. Doubling the sampling bandwidth through time alternation is beneficial for many applications. For example, a radio transceiver architecture can increase the number of information signal carriers, thereby increasing the system data output. Doubling the sampling frequency can also improve the resolution of LIDAR measurement systems using the time-of-flight (TOF) principle. In fact, the uncertainty of the TOF measurement value can be reduced by shortening the effective sampling period.

Digital oscilloscopes also require a high sampling frequency Fs/input frequency FIN ratio to accurately acquire complex analog or digital signals. To acquire the harmonic portion of the input frequency, the sampling frequency must be a multiple of the input frequency (maximum). For example, if the oscilloscope sampling frequency is not high enough and the higher-order harmonics are outside the Nyquist bandwidth of the analog-to-digital converter, a square wave will appear as a sine wave.

Figure 1 illustrates the benefit of doubling the sampling frequency of the oscilloscope front end. The 6GSPS sampled waveform is a more accurate representation of the sampled analog input. Many other test instrumentation systems (such as mass spectrometers and gamma-ray telescopes) rely on higher oversampling/FIN to make pulse waveform measurements.

Figure 1: Time domain plot of 247.77MHz signal sampled at 3GSPS and 6GSPS.

Increasing the sampling frequency has other advantages as well. Oversampling the signal also achieves the characteristic of improved gain in the digital domain through digital filtering. In effect, the ADC noise floor can be spread over a larger output bandwidth. Doubling the sampling rate for a fixed input bandwidth provides a 3dB improvement in dynamic range. Each doubling of the sampling frequency provides an additional 3dB of dynamic range.

Difficulties of Time Interleaving

The main difficulty of time interleaving is the precise calibration of the sampling clock edges between channels and the compensation of the inherent variations between ICs. Accurately matching the gain, offset and clock phase between the individual analog data converters is a significant challenge, primarily because these parameters are frequency dependent. Unless these parameters can be accurately matched, dynamic performance and resolution will be degraded. Figure 2 shows the three main sources of error.

Figure 2: Gain, offset, and timing errors produced by interleaving ADCs.

Sampling Clock Phase Adjustment

Typically, a dual-channel interleaving converter system requires the timing of the ADC input sampling clock to be shifted by 1/2 clock period. However, the ADC083000 architecture uses on-chip interleaving with a clock frequency equal to half the sampling rate, or 1.5 GHz for 3 GSPS. Therefore, for a dual-channel system using two ADC083000s, the ADC input sampling clock edges must be shifted by 1/4 clock period or staggered by 90 (1/4 clock period). That is, a 1.5 GHz clock corresponds to 166.67 ps. The clock

signal trace length that corresponds to a 1/4 clock period phase shift can be calculated relatively accurately. For FR4 printed circuit board material, signals propagate at a speed of 20 cm/ns (50 ps is 1 cm). For example, if the clock trace to one ADC is 3 cm longer than the other, this will produce a phase shift of 150 ps. The difficulty lies in accurately matching the additional 16.67 ps time shift.

The ADC083000 has an integrated clock phase adjustment feature that allows the user to add delay to the input sampling clock to achieve a phase shift relative to the sampling clock of the other ADC. The ADC clock phase can be manually adjusted using two internal registers via the SPI bus. Phase shift can only be achieved in one direction, adding delay. The designer should determine the position of the two discrete ADCs, determine which one is "in front" and adjust its phase so that its sampling edge is 90 degrees with the other ADC sampling edge, so that sub-picosecond adjustment resolution can be achieved.

Inter-channel gain and offset matching

In a dual converter interleaving system, the error voltage generated by channel gain mismatch will cause image spurious signals at Fs/2-FIN and Fs/4±FIN (assuming the input signal is within the first Nyquist band). An 8-bit converter has 28 or 256 codes. Assuming the full converter input range is Vp-p, the LSB size is equal to 1V/256=3.9mV. We can deduce that the gain matching required for 1/2LSB accuracy is 0.2%.

The input full-scale voltage or gain of the ADC083000 can be adjusted linearly and monotonically using 9-bit data resolution. The adjustment range is ±20% of the nominal 700mVp-p differential value, or 560mVp-p to 840mVp-p.

840mV-560mV=280mV.

29 = 512 steps

280mV/512 = 546.88μV

This fine adjustment allows for 0.2% greater gain matching than required above.

Offset mismatch between adjacent channels will generate an error voltage resulting in an offset spur at Fs/2. Since the offset spur is at the edge of the Nyquist band, designers of dual-channel systems can usually plan the system frequency accordingly and focus on gain and phase matching.

However, assuming that the required offset matching is also 1/2LSB, the input offset of the ADC083000 can be linearly and monotonically adjusted from a nominal zero offset to a 45mV offset using 9-bit resolution. Therefore, each encoding step provides 0.176mV offset, and 9-bit resolution achieves 1/2LSB accuracy.

Synchronization of Digital Outputs

Synchronization of the data streams output from the two ADCs is critical to achieving the best combination of sampling speed and bandwidth. That is, if the outputs are not synchronized between the converters, no meaningful data can be acquired. Gigabit sampling rate ADCs can demultiplex the output data to reduce the digital output data rate. The user can choose to split the data rate to 1/2 or 1/4, depending on the processing power of the FPGA technology used.

The output acquisition clock (DCLK) is also split and can be configured in SDR or DDR mode. However, demultiplexing introduces new considerations because there is now an added uncertainty in the coordination between the input sampling clock and the DCLK outputs of each ADC. To overcome this problem, the ADC083000 can accurately reset the relationship between the sampling clock input and the DCLK output, which is determined by the user-supplied DCLK_RST pulse. This allows multiple ADCs to be used in a system and have their DCLK (and data) outputs transition at the same time as the sampling shared input clock, thereby achieving synchronization between multiple ADCs. Digital Alternation Method

Analog calibration is a proven method to achieve high dynamic range and high overall integration solutions, and its integrated clock phase, gain and offset adjustment functions provide high accuracy. A

viable alternative to analog calibration is a digital correction algorithm for alternating data. This method seeks to correct data converter mismatches in the digital domain without the need for any analog offset, gain or phase correction. In theory, these algorithms can work independently without the need to implement calibration or understand the input signal. In addition, the convergence time of digital offset, gain and phase correction factors is also a key system metric.

An algorithm developed by SP Devices has been proven to be a digital post-processing method that meets these conditions. SP Devices' ADX technology continuously provides background estimates of the gain, offset and time deviation errors of the analog-to-digital converter without the need for any special calibration signals or post-trim. This algorithm is effective for correcting static and dynamic mismatch errors. The

ADX technology estimates the error and reconstructs the signal with all mismatch errors suppressed. The IP-core's error correction algorithm is effective for any input signal type. The result of this digital signal processing exceeds the time-interleaved spectrum of the ADX core and eliminates the obvious interleaved distortion spurs associated with mismatch. The

National Semiconductor reference board equipped with two ADC083000 3GSPS, 8-bit analog-to-digital converters demonstrates the SP Devices algorithm. The data converters are interleaved using the ADX technology embedded in the board's FPGA. Figure 3 shows the block diagram of the 7GSPS digitizer card.
 

Figure 3: ADQ108 system block diagram with LMX2531 and LMH6554.

Figure 4 is the output spectrum performance diagram of the SPDevicesADQ108 data acquisition card. It is worth noting that the spurious peak is partly due to harmonic distortion, and the alternating spurious signal has been greatly reduced.

Figure 4: ADC combined spectrum using ADX technology.

Ultra-High Speed ​​ADC Support Circuitry

To achieve the advanced performance that can be achieved using data converters such as the ADC083000, it is necessary to ensure that the support circuitry has performance that matches the data converter itself. Key elements of the support circuitry include:

1) A high performance, low jitter clock source.

2) A high linearity, low noise amplifier or balun to drive the ADC input.

It is recommended to use the LMX2531 or LMX2541 clock synchronizer to generate the low jitter ADC clock signal and the LMH6554 to drive the ADC analog input.

The LMX2531 integrates a phase-locked loop (PLL) and VCO and provides a noise floor of better than -160dBc/Hz. Multiple versions of the chip are available to accommodate different frequency bands from 553MHz to 2790MHz.

To achieve better SNR performance at high input frequencies, it is recommended to use the lower phase noise LMX2541 as a suitable clock source. The LMX2541 has a noise of less than 2 milliradian angle (mrad) RMS at 2.1GHz and less than 3.5mrad RMS at 3.5GHz. The LMX2541's phase-locked loop has a corrected noise floor of -225dBc/Hz and can operate at a maximum phase detection rate (comparison frequency) of 104MHz in integer and fractional modes.

The LMH6554 is the industry's highest performance differential amplifier. The low impedance differential output of the LMH6554 can be used to drive the analog-to-digital converter input and any intermediate filtering stage. This wideband fully differential amplifier can drive 8-bit to 16-bit high-speed analog-to-digital converters, with 0.1dB gain flatness below 800MHz, 72dBcSFDR at 250MHz, and low input voltage noise performance of 0.9nV/sqrtHz.

The LMH6554 has 16-bit linearity below 75MHz and can drive 2V peak-to-peak voltage to a minimum 200 ohm load. The LMH6554 can be used in either differential-to-differential or single-ended-to-differential configurations with external gain setting resistors and integrated common-mode feedback. The amplifier offers large signal bandwidth up to 1.8GHz, 8dB noise, and 6200V/μs slew rate.

Figure 5 shows a typical application block diagram using the above support components.

Figure 5: Typical system block diagram.

Summary

This article has described the challenges of interleaving high-speed analog-to-digital converters and several methods to address these issues. Due to advances in interleaving techniques, low-jitter clock sources, and high-performance amplifiers, it is now possible to achieve excellent dynamic performance that maintains over 6GSPS.