A novel design scheme for bandwidth-adaptive all-digital phase-locked loop

This scheme adopts the method of combining theoretical analysis with hardware circuit design to design the system, and implements it with FPGA. The system simulation and hardware circuit test results confirm the correctness of the design scheme. The free oscillation frequency of the phase-locked loop can change with the change of the input signal frequency. It has the characteristics of simple circuit structure, wide phase-locking range, fast locking speed and small steady-state error.

0 Introduction

The phase-locked loop is a closed-loop automatic control system whose output signal can track the phase of the input signal. Due to its unique and excellent performance, it has been widely used in the fields of communication, radar, measurement and automatic control.

Compared with the analog phase-locked loop, the all-digital phase-locked loop (ADPLL) has the characteristics of high reliability, stable parameters and easy integration. Therefore, it has been studied more and more widely and has become an indispensable component in various electronic devices.

The phase-locked loop has three important performance indicators: phase-locking range, phase-locking speed and stability. In order to improve the performance indicators of the phase-locked loop, some scholars have conducted in-depth analysis and research.

This paper proposes a composite control method based on adaptive proportional integral to overcome the problem of mutual constraints between the phase-locking range, phase-locking speed and stability of the phase-locked loop.

1 Structure and working principle of the all-digital phase-locked loop

The system consists of four modules: digital phase detector, adaptive controller, digital filter and digitally controlled oscillator, as shown in Figure 1. The working principle of each module is introduced in detail below.

The ADPLL uses a dual D-type trigger digital phase detector. The phase detector compares the phase of the input signal and the output signal, and outputs a signal sub (add) that reflects the phase advance (or lag). Sub and add not only reflect the phase advance and lag, but also their pulse width reflects the size of the phase error. Its structural block diagram is shown in Figure 2.

The adaptive controller module mainly plays the role of adjusting the loop bandwidth. On the one hand, the controller discriminates the input signal, and on the other hand, quantizes the phase error signals sub and add. The filter control parameter M is calculated according to the quantized value. If the frequency of the input signal changes significantly, the controller sends a control signal sig, assigns the control parameter M to the filter, and performs initial setting on the periodic reset reversible counter and the non-reset reversible counter, so as to quickly achieve frequency capture and loop bandwidth adjustment.

The loop filter is mainly composed of a periodic reset reversible counter and a non-reset reversible counter, in which the system high-frequency clock clk is its synchronous clock signal, and add and sub are used as the add and subtract count enable control signals of the two counters. When the count enable signal is high, the two counters perform corresponding add 1 or subtract 1 operations when the clk clock rises, and keep the count value unchanged when the count enable is low. When the input signal fin rises, the count values ​​of the two counters are shifted and added, and the addition result is sent to the latch as the control parameter N of the numerically controlled oscillator, and then the proportional counter is reset.

The digital control oscillator module uses a divide-by-N counter digital control oscillator, which works under the control of the system high-frequency clock clk. The frequency division parameter N comes from the output value of the loop filter. If the counter count value is less than N, the counter will add 1 every time the clk rising edge arrives. When the count reaches N, the counter is reset and the output fout is inverted.

2 System Modeling and Analysis

From the above analysis, it can be seen that when the input signal changes near the locking frequency point, the mathematical model of the phase-locked loop can be represented by Figure 3.

In Figure 3, θin (s) is the phase of the input signal fin, θout (s) is the phase of the digital voltage-controlled oscillator output signal fout; Kdpd (s), Kdlf (s), and Kdco (s) are the transfer functions of the digital phase detector link, the digital filter link, and the digital voltage-controlled oscillator link, respectively.

2.1 System mathematical model

Assuming that the system high-frequency clock signal is fclk, the transfer function of the phase detector module can be obtained from the working principle of the dual D-flip-flop phase detector:

Where: K1, K2 are the control parameters of the filter, ωin is the angular frequency of the input reference signal. If K1 and K2 are fixed constants, then equation (6) satisfies the bandwidth adaptive control law proposed in the literature [10], that is, it satisfies the following equation:

Formula (10) shows that the adjustment time of the system is proportional to the period of the input signal, which is consistent with the bandwidth adaptive control law formula (7). According to formula (10), (11), appropriate C1 and C2 can be selected to ensure good dynamic performance of the system. From formula (12), it can be seen that increasing the system high-frequency clock frequency fclk can reduce the steady-state error of the system.

3 System simulation and experiment

This design uses Verilog HDL hardware description language for circuit design, and uses Altera's QuartusⅡ software as the design platform. Finally, the EP1C6Q240C8 FPGA device is used to implement the hardware circuit, where the system clock frequency of the chip is 20 MHz. Select the control parameters C1 = 0.113, C2 = 0.707, at this time the loop filter control parameters K1 = 2-1, K2 = 2-2, the system response time ts is about 6 input signal cycles; the overshoot Mp% is 4.32%; the frequency tracking lock range is designed to be 76.3 Hz~78.1 kHz.

3.1 Simulation waveform and analysis

The simulation waveform of the phase-locked loop designed in this paper is shown in Figures 4 and 5.

 

It can be seen from the simulation waveform Figure 4 that when the input signal phase jumps 180°, the phase-locked loop can achieve phase relocking in about 7 cycles. It can be seen from Figure 5 that when the input signal frequency changes suddenly, the system can also quickly achieve relocking.

3.2 Hardware Measured Waveform and Analysis

The hardware measured waveform is shown in Figure 6.

From the measured waveform, it can be seen that the system has the advantages of wide phase-locked range and small steady-state error.

4 Conclusion

The design of the fully digital phase-locked loop based on the adaptive proportional integral composite control method proposed in this paper can realize real-time control of the loop, and its free oscillation frequency can change with the change of the input signal frequency, overcoming the defects of the traditional phase-locked loop. It has the advantages of simple circuit structure, wide phase-locked range, fast locking speed, and small stable error. It can be embedded in the digital system chip as a functional module and has a very wide range of uses.