Design of X-ray Spectrum Data Acquisition System Based on DSP

X-rays are generated by high-energy electrons moving at a reduced speed in matter or by the transition of electrons in the inner orbit of atoms, so they have strong penetrability and are widely used in many aspects such as ray detection and medium identification. When the ray energy is constant, the attenuation of the X-ray radiation intensity is only related to the medium it passes through, that is, when X-rays penetrate different media, the transmission intensity is different. Therefore, the intensity of detected X-rays can be analyzed to conduct relevant research on medium identification.

X-ray detection is achieved by detecting the intensity of the rays after the detector receives them through the material. This paper uses a scintillation detector composed of NaI (Tl) crystal and photomultiplier tube for X-ray detection. The pulse signal amplitude output by the detector is proportional to the intensity of the transmitted rays, so the analysis of the pulse signal amplitude provides important information for medium identification. This paper selects the high-speed DSP chip TMS320F2812 as the main controller to complete the analysis and processing of the pulse signal amplitude.

1 System overall framework design

The intensity of X-rays detected by the scintillation detector is generally weak, and needs to be pre-processed by amplification, filtering, peak holding, etc., and then the DSP is used to perform A/D conversion, pulse amplitude analysis, data storage, and communication with the host computer on the processed signal, and finally a spectrum line diagram of the X-ray intensity is drawn. The X-ray energy spectrum data acquisition system is mainly composed of five parts: preamplifier circuit, filter circuit, main amplifier circuit, peak holding circuit, DSP main control circuit, and its overall block diagram is shown in Figure 1.

2 Design of system components

2.1 Design of preamplifier circuit

The preamplifier circuit is the key to the design of the entire pre-stage preprocessing circuit. Under unshielded conditions, the transmitted X-rays are generally in the background noise of transformer electromagnetic radiation, power frequency interference, background radiation, etc. In order to extract the X-ray intensity carrying the identification medium information from the strong background noise, the entire X-ray energy spectrum data acquisition system needs to have high performance, and the preamplifier circuit is an important part of the front end of the pre-stage preprocessing circuit, so the preamplifier circuit designed in this system is shown in Figure 2. The differential operational amplifier has a high common mode rejection ratio, which can suppress the errors introduced by various common mode interferences.

The circuit designed in Figure 2 consists of three basic operational amplifiers, among which operational amplifiers A1 and A2 form the first stage of parallel input amplification to improve the input impedance and gain of the amplifier, and A3 is a differential amplifier, which serves as the second stage of the amplifier. The common mode rejection ratio of the entire circuit depends on the degree of symmetry of A1 and A2 in the first stage amplification circuit, and the common mode rejection ratio of the second stage amplification circuit depends on the closed loop gain of the differential operational amplifier A3 and the matching accuracy of the resistors. From Figure 2, it can be calculated that the output voltage of the preamplifier circuit is Uo. When Ui1=Ui2, the current in R2 is zero, so the output voltage Uo=0. It can be seen that the circuit amplifies the differential mode signal and suppresses the common mode signal.

2.2 Design of filter circuit

Since the noise and signal are amplified at the same time, it is not conducive to the work of the subsequent amplifier circuit, so the signal needs to be filtered after being amplified by the preamplifier circuit. In order to ensure the accuracy of X-ray detection, a bandpass filter circuit composed of a voltage-controlled voltage source second-order high-pass filter and a second-order low-pass filter circuit in series can be designed after the preamplifier circuit as shown in Figure 3.

Figure 3 is the designed bandpass filter circuit, which consists of active high-pass and active low-pass filters in series, and its bandwidth range is 100 kHz~1 MHz. The operational amplifiers for high-pass and low-pass filters use the dual operational amplifier chip LM358 with high precision, low bias and low power consumption. According to the rapid design theory of active filter circuits, the various parameters of high-pass and low-pass filters can be obtained.

The in-band gain of the high-pass filter is 1, the cut-off frequency is 100 kHz, and the parameters of the high-pass filter are: C1=C2=800 pF, R1=R2=20 kΩ; the in-band gain of the low-pass filter is 1, the cut-off frequency is 1 MHz, and the parameters of the low-pass filter are: C3=C4=1 nF, R3=R4=160 Ω.

2.3 Design of the main amplifier circuit

The signal after pre-amplification and bandpass filtering is still relatively weak, with the largest pulse amplitude being about 400 mV and being a negative pulse. Since the input range of the subsequent ADC circuit is 0~3.3 V, the pulse signal needs to be further amplified before being sent to the ADC circuit. The designed main amplifier circuit is shown in Figure 4.

As shown in Figure 4, the main amplifier circuit uses a single operational amplifier chip OP37 with low noise, wide bandwidth and high precision to form a voltage parallel negative feedback circuit. In order to make the back-end A/D conversion circuit have a more ideal input signal, the voltage amplification factor of the main amplifier circuit is designed to be 6~8 times. Therefore, the parameters of each resistor in the figure are designed as: R1=25 kΩ, R3=30 kΩ, R4=200 kΩ, and R2 uses an adjustable potentiometer with a nominal resistance of 10 kΩ. In addition, in order to avoid the burrs in the circuit causing the output of the amplifier circuit to exceed the input voltage range of the ADC, a bidirectional limiting circuit is designed at the output end of the main amplifier circuit. When the output of the main amplifier circuit is higher than UMax, the diode D1 is turned on, and the output voltage is limited to UMax; when the output of the main amplifier circuit is lower than UMin, the diode D2 is turned on; by selecting appropriate UMax and UMin, the output voltage can be clamped at 0~3.3 V, meeting the range requirements of the input voltage of the A/D conversion circuit.

2.4 Design of Peak Hold Circuit

Although the amplitude of the pulse signal after being processed by the main amplifier circuit is relatively ideal, the pulse width is still small, with a minimum pulse width of only 1 ms. A/D conversion requires a certain amount of time. To sample the peak of the pulse, the peak voltage needs to be maintained, and an interrupt request signal is sent to the DSP at the same time, so that the DSP responds to the interrupt and starts the A/D conversion. After the conversion is completed, the DSP restores the sample and holder to the sampling state to realize the logical control of the system. The peak hold circuit designed in this article is shown in Figure 5.

As shown in Figure 5, U4 is the chip LF398, which is an integrated sample-and-hold developed by a US semiconductor company. It only needs an external holding capacitor to complete the sample-and-hold function, and its sample-and-hold control terminal can be directly connected to TTL, CMOS logic levels. U1 and U2 are high-speed voltage comparators LM311, U3 is a rising-edge-triggered dual D flip-flop, and U5 is an AND gate 74LS08. The pulse signal processed by the main amplifier circuit is input to the threshold comparator U1, and the other is input to the peak detection circuit composed of comparator U2 (R3C1 forms a delay circuit to compare with the pulse signal input from the reverse input terminal of U2 to determine whether the peak of the pulse signal has arrived), and another is input to the sample-and-hold LF398, and the output of LF398 is connected to the ADCINA0 pin of the ADC module in the DSP.

When the voltage pulse signal amplitude is greater than the threshold voltage Vref (Vref is set to 0.5 V during debugging, and voltages below 0.5 V can be considered noise and not considered), comparator U1 outputs a high level, generating a rising edge, which triggers U3A again, and its Q terminal outputs a high level. When the peak value arrives in the future, the Qˉ terminal of U3B is ANDed to obtain a high level, which controls the sampling control terminal of LF398 to enter the sampling state. When the pulse signal reaches the peak value, comparator U2 outputs a high level, and a rising edge is obtained. The rising edge triggers U3B again, and its Qˉ terminal outputs a low level, and U5 outputs a low level, and LF398 enters the holding state. The falling edge of the Qˉ output of U3B serves as the start signal of the DSP capture unit CAP3 interrupt. CAP3 sends a signal to start the ADC. When the A/D conversion is completed, the DSP's GPIO port outputs a low level as the clear signal CLR of U3. After the dual D flip-flop 74LS74 is cleared, the sampling control end of LF398 re-enters the sampling state, ready to maintain the peak value of the next pulse.

2.5 Design of DSP Program Flow

The control of A/D conversion and pulse amplitude analysis is the core part of the entire X-ray energy spectrum data acquisition system, which determines the accuracy of energy spectrum data acquisition and the performance of the entire system. Since the minimum pulse width of X-rays detected by the NaI detector is only 1 ms, the instruction cycle of the general single-chip microcomputer is in the microsecond level, so it cannot meet the application requirements. In this design, the high-speed DSP chip TMS320F2812 is selected, with a clock frequency of up to 150 MHz and a clock cycle of 6.67 ns, so that a series of operations such as A/D conversion, classification of conversion results by amplitude, and counting can be completed within the time of a pulse width; and the on-chip ADC module is a 12-bit resolution, pipelined analog/digital converter with a total of 16 sampling channels and a maximum sampling frequency of 12.5 MSPS; the chip can support up to 96 internal peripheral interrupts, one of which can be used to start A/D conversion.

As shown in Figure 5, when the sample-and-hold LF398 enters the holding state from the sampling state, the Qˉ output of the rising edge trigger U3B changes from a high level to a low level, thereby generating a falling edge. When the DSP event manager EV capture unit CAP3 captures this falling edge, it sends a signal to start the ADC and enter the A/D interrupt. At this time, the high-speed A/D converter begins to convert the DC level held by the sample-and-hold LF398 into a 12-bit digital signal, and the conversion result is stored in the result register of the ADC module; at the same time, the DSP will perform internal RAM addressing based on this result, and add 1 to the corresponding channel address. Then the DSP generates a low-level signal through the general input/output multiplexer GPIO, and this low-level signal is input to the clear end of U3, so that LF398 enters the sampling state again. During the DSP programming process, a certain time for collecting energy spectrum data is pre-set. When the specified time comes, the DSP transfers the collected energy spectrum data to the external Flash memory and clears the energy spectrum data stored in the internal RAM for the next collection. The software flow of DSP processing in this article is shown in Figure 6.

3 System debugging results

When the hardware circuits of each part of the X-ray spectrum data acquisition system are successfully debugged, it is necessary to coordinate the system with the NaI (Tl) detector. The X-ray generator generates X-rays by applying 80 kV high voltage to the X-ray tube. After the NaI (Tl) detector detects the X-rays, it generates a voltage pulse signal through the internal photomultiplier tube. This pulse signal is gradually processed by the hardware circuits of each part of the system, and then uploaded to the computer for analysis and processing through the serial communication interface SCI of TMS320F2812, and finally draws the X-ray spectrum. The debugging of the system results is completed in TI's integrated development environment CCS3.3. The graphic display window of CCS3.3 is called, and the energy spectrum drawn is shown in Figure 7.

As shown in Figure 7, the number of channels in this paper is set to 1024. Since the ADC of TMS320F2812 is 12 bits, the data after A/D conversion needs to be shifted right by 2 bits. The counting rate of each channel of the entire spectrum line is very low. The channel with the largest counting rate is around 250 channels, and the counting rate does not exceed 30. In order to increase the channel counting rate and obtain a more ideal spectrum line, the power supply voltage of the X-ray tube can be further increased or the filament current can be increased.

4 Conclusion

This proposal designs an X-ray energy spectrum data acquisition system based on the DSP chip TMS320F2812. The proposal introduces the hardware circuit and software design for energy spectrum data acquisition. The debugging results show that the system circuit designed in this proposal is simple, has good performance and strong data acquisition and processing capabilities. When used in conjunction with a scintillation detector composed of a NaI (Tl) crystal and a photomultiplier tube, it has achieved good results. At the same time, this system has the characteristics of small size, low power consumption, stable output, etc., and has certain application value.