Design and implementation of a large-capacity FPGA with 6.8 billion transistors

Not long ago, Xilinx launched the industry's largest programmable logic device, the Virtex-7 2000T  FPGA , and began to supply it to customers. The Virtex-7 2000T has 6.8 billion transistors and 2 million logic cells, equivalent to a 20 million-gate ASIC. This is also Xilinx's first FPGA that uses the unique stacked silicon interconnect (SSI) technology.

Analysis of stacked silicon wafer interconnect architecture

Xilinx is the first company to use stacked silicon interconnect (SSI) technology to make commercial FPGAs. Tang Liren, the company's global senior vice president and executive president of the Asia-Pacific region, said that the application of SSI technology has made Xilinx's large-capacity FPGAs a reality, and the pioneering application of 2.5D IC stacking technology has enabled Xilinx to provide customers with twice the capacity of similar competing products and exceed the development speed of Moore's Law.

Tang Liren believes that without SSI technology, it would take at least until the next generation of process technology to achieve such a large transistor capacity in a single FPGA. In terms of the launch of a new generation of products, SSI delivered Xilinx's largest 28nm device to customers at least one year in advance, which is especially important for ASIC and ASSP simulation and prototyping.

Tang Liren introduced that 2.5D chip stacking technology refers to stacking active chips on passive devices, which is the stacking of active chips and passive chips; while 3D chip stacking technology refers to stacking active chips on active chips, which is the stacking of active chips and active chips. The 2.5D stacking technology created by Xilinx is to place several silicon slices (active slices) side by side on a passive silicon interposer, and the slices are then connected by metal passing through the interposer, similar to the way different ICs on a printed circuit board communicate through metal interconnects. Xilinx has built the industry's largest capacity programmable logic device by interconnecting four different FPGA chips on a passive silicon interposer, solving the manufacturing challenge of defect-free large single chips.

In addition, because the chips are placed side by side on the silicon interposer, SSI technology can avoid the power consumption and reliability issues caused by stacking multiple chips. The interposer provides more than 10,000 high-speed interconnects between each chip, which can support the high-performance integration required for various applications.

It is understood that the real advantage of SSI technology is that although 2000T is composed of 4 slices, it still maintains the traditional FPGA usage mode, and designers can program the device as a very large FPGA through Xilinx tool flow and methods. In this way, designers can design the required products conveniently and clearly, and adopting this architecture can save a lot of space, and designers can add the required devices as needed.

The Virtex-7 2000T FPGA launched by Xilinx this time  uses 2.5D IC stacking technology instead of the 3D IC technology mentioned earlier. Tang Liren explained: "Xilinx is also optimistic about the prospect of full 3D IC stacking technology without an interposer, but 3D IC technology currently faces many challenges. It will take a longer time for the technology to be standardized in the entire industry. It will take another 2 to 3 years for 3D to truly achieve mass production."

Tang Liren said that the adoption of SSI technology has put Xilinx ahead of FPGA manufacturers and enabled Xilinx to develop devices faster than Moore's Law.

In addition to 6.8 billion transistors and 2 million logic cells, the Virtex-7 2000T  FPGA also includes 305,400 configurable logic blocks (CLBs) and a distributed RAM capacity of up to 21,550KB. It has a total of 2160 DSP slices, 46,512 BRAMs, 24 clock management modules, 4 PCIe modules, 36 GTX transceivers (each with a performance of 12.5Gbps), 24 I/O banks, and 1200 user I/Os. In terms of reducing power consumption, Xilinx uses a 28nm HPL process, which consumes 5W in static mode and only 19W in operation.

Tang Liren told reporters that at the 28nm process technology node, the NRE of ASIC or ASSP exceeds 50 million US dollars, and ASIC modification may increase the cost by nearly half. Therefore, unless it is for the most stable high-volume market applications, ASIC and ASSP designs will only be adopted less and less. In addition, market pressures such as competition and shortening product time to market have also brought challenges to the development of custom ASICs. In this case, replacing ASIC with a Virtex-72000T device can achieve the required system performance and functions. For example, customers use Xilinx Virtex-7 2000TFPGA to replace large-capacity ASICs, and can increase development time by 2/3 (ASIC development time is up to 3 years) with the same overall investment cost; at the same time, create an integrated system, increase system bandwidth, and thus avoid I/O interconnection and significantly reduce power consumption. In addition, it can also accelerate the prototyping and simulation of advanced ASIC systems.

At this point, designers can focus on designing without having to worry about small mistakes that will lead to catastrophic rework. In addition, the Virtex-7 2000T is reprogrammable, so if designers make a mistake, they can just reprogram the device.

Currently, SSI technology has become a part of Xilinx's strategic planning. In the coming year, Xilinx also plans to launch the Virtex-7 HT  FPGA series and SSI configuration through technological innovation.