Explain in detail the fundamental differences between JLINK and JTAG

To debug ARM , you must follow the ARM debug interface protocol, and JTAG is one of them. When simulating, IAR, KEIL, ADS, etc. all have a common debug interface, and RDI is one of them. So how do we complete the conversion from RDI to ARM debug protocol (JTAG)? There are two ways:

1. Write a service program on the computer to parse the RDI commands in IAR, KEIL and ADS into the relevant JTAG protocol, and then send it to your target board through a physical conversion interface (note that this conversion is only a conversion on the electrical physical layer, just like the function of RS232). H-JTAG is like this. The hardware of H-JTAG is just a physical level conversion interface, so it is very simple. The h-JTAG software installed in the computer is the service program mentioned above, which is responsible for protocol conversion.

2. Make a board to directly receive debugging commands from IAR, KEIL, ADS and other software, and use this board to convert RDI->JTAG protocol. Then communicate with the target board, which is the working principle of JLINK.

From the above, we can see that H-JTAG is slower because it uses software to convert protocols, but the hardware is simple. The second method, JLINK, generally has a powerful CPU to convert hardware protocols, which makes the hardware complex but fast.

Basic Principles of JTAG

JTAG (Joint Test Action Group) is an international standard test protocol (IEEE1149.1 compatible). The standard JTAG interface is 4 lines - TMS, TCK, TDI, TDO, which are mode selection, clock, data input and data output lines respectively.

There are two main functions of JTAG, or there are two main categories of JTAG:

1) One type is used to test the electrical characteristics of the chip to detect whether there is a problem with the chip;

2) Another type is used for debugging, debugging various chips and their peripheral devices; a CPU with a JTAG Debug interface module can access the CPU's internal registers, devices hanging on the CPU bus, and registers of built-in modules through the JTAG interface as long as the clock is normal. This article mainly introduces the Debug function.

JTAG Principle Analysis

Simply put, the working principle of JTAG can be summarized as: define a TAP (Test Access Port) inside the device, and use a dedicated JTAG test tool to test and debug the internal nodes. First, the basic concepts and contents of boundary scan and TAP are introduced.

Boundary Scan

The basic idea of ​​boundary scan technology is to add a shift register unit, namely boundary scan register, close to the input/output pins of the chip.

When the chip is in the debugging state, the boundary scan register can isolate the chip from the peripheral input/output. Through the boundary scan register unit, the chip input/output signals can be observed and controlled. For the input pin of the chip, the signal (data) can be loaded into the pin through the boundary scan register unit connected to it; for the output pin of the chip, the output signal on the pin can also be "captured" through the boundary scan register connected to it. Under normal operating conditions, the boundary scan register is transparent to the chip, so normal operation will not be affected in any way. In this way, the boundary scan register provides a convenient way to observe and control the chip that needs to be debugged. In addition, the boundary scan (shift) register units on the chip input/output pins can be connected to each other to form a boundary scan chain (Boundary-ScanChain) around the chip. The boundary scan chain can be serially input and output, and the chip in the debugging state can be easily observed and controlled through the corresponding clock signal and control signal.

Test access port TAP

TAP (Test Access Port) is a general port. Through TAP, all data registers (DR) and instruction registers (IR) provided by the chip can be accessed. The control of the entire TAP is completed by the TAP controller (TAPController). The following will introduce several interface signals of TAP and their functions. Among them, the first four signals are mandatory in the IEEE1149.1 standard.

TCK: Clock signal, provides an independent, basic clock signal for TAP operation.

TMS: Mode selection signal, used to control the transition of the TAP state machine.

TDI: data input signal.

TDO: data output signal.

TRST: Reset signal, which can be used to reset (initialize) the TAPController. This signal interface is not mandatory in the IEEE1149.1 standard, because the TAPController can also be reset through TMS.

STCK: Clock return signal, not mandatory in the IEEE1149.1 standard.

Simply put, PC debugging of the target board is to access the relevant data register (DR) and instruction register (IR) through the TAP interface.

After the system is powered on, TAPController first enters the Test-LogicReset state, then enters the Run-Test/Idle, Selcct-DR- Scan, Select-IR-Scan, Capture-IR, Shift-IR, Exitl-IR, Update-IR states in sequence, and finally returns to the Run-Tcst/Idle state. In this process, the state transfer is driven by the TCK signal (rising edge), and the TAP state is selected and converted by the TMS signal. Among them, in the Capture-IR state, a specific logic sequence is loaded into the instruction register; in the Shift-IR state, a specific instruction can be sent to the instruction register; in the Update-IR state, the instruction just entered into the instruction register will be used to update the instruction register. Finally, the system returns to the Run-Test/Idle state, the instruction takes effect, and the access to the instruction register is completed. When the system returns to the Run-Test/Idle state, the required data register is selected according to the content of the previous instruction register, and the work on the data register begins. The basic principle is exactly the same as the access to the instruction register, which is sequentially select-DR-Scan, Capture-DR, Shift-D, Exit-DR, Update-DR, and finally returns to the Run-Tcst/Idle state. Through TD1 and TDO, new data can be loaded into the data register. After one cycle, the data in the data register can be captured, and the data update of the chip pins connected to each register unit of the data register is completed, and the access to the data register is also completed.

At present, there are two types of JTAG interfaces on the market: 14-pin and 20-pin. Among them, 20-pin is the mainstream standard, but there are also a few target boards that use 14-pin. After a simple signal conversion, they can be used interchangeably.