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Problem with conditional execution with $value$plusargs [Copy link]

I am following the example on page 115 of Xia Yuwen's book.
The code is as follows:

`timescale 1 ns/ 1 ps
module seven_vlg_tst();
// constants                                           
// general purpose registers
reg eachvec;
// test vector input registers
reg clk;
reg rst_n;
// wires                                               
wire led;

// assign statements (if any)                          
seven i1 (
// port map - connection between master ports and signals/registers   
	.clk(clk),
	.led(led),
	.rst_n(rst_n)
);


reg[8*128-1:0] test_string="test1.vec";

reg[7:0] vectors[0:18];
integer clk_period;
reg[4:0] i;
reg j=0;
//test_string<="test1.vec";

	

initial begin
	if($value$plusargs("filename=%s",test_string))
	begin
		
		
		$readmemh(test_string,vectors);
		for(i=0;i<16;i=i+1)
			$display("%h",vectors[i]);
	end
	else
		$display("Test name option not specified");
		
	if($value$plusargs("clk_t=%d",clk_period))
		begin
			j=1;
			clk=0;
			forever #(clk_period/2) clk=~clk;
			
	   end 
	else
		$display("Clock period option name not specified");
end

 initial begin
		  
		if(j==1)
			begin
			rst_n=0;
			#1000;
			rst_n=1;
			#5000;
			$stop;
			end
		end 

                                              
endmodule

The simulation phenomenon is as follows:

The data is read out, but there is no waveform.
Can an expert tell me how to solve this problem? Thank you!

This post is from EE_FPGA Learning Park
Personal signature为江山踏坏了乌骓马,为社稷拉断了宝雕弓。
 

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