Design of frame synchronization system based on FPGA

The frame synchronization system designed in the scheme was implemented on Xilinx FPGA device XC3S200-4FT200, and the simulation test was carried out using Modelsim 6.0 software. The simulation results show that the synchronization system designed in this scheme works stably and meets the performance requirements.

0 Introduction

In digital communication systems, the transmitter generally uses a certain number of code elements to form "words" or "sentences", that is, to form data frames for transmission, so the frame is the basic unit of data transmission. Different communication systems have different frame structures. The frame is generally divided into two parts: frame synchronization code and data. The frame synchronization code is used to mark the starting position of the frame; the data is the valid code element that needs to be transmitted. There are two main methods for inserting frame synchronization code groups: centralized insertion method and interval insertion method. The centralized insertion method is a method of inserting frame synchronization code groups at the beginning of each frame; the interval insertion method is to insert frame synchronization code groups into the data stream in a dispersed manner, that is, insert a frame synchronization code element every certain number of information code elements. This paper mainly proposes a design scheme for FPGA frame synchronization using centralized insertion method.

Generally speaking, frame synchronization can only be performed after bit synchronization. Although the frequency of the signal can be easily obtained by dividing the bit synchronization signal, the start and end times of the frame cannot be determined by dividing the bit synchronization signal. The main task of frame synchronization is to obtain the start and end positions of each data frame. With the development of programmable logic devices, the use of FPGA to implement digital systems such as frame synchronization has a series of advantages such as fast speed, easy use, and programmable configuration of various parameters, and has therefore been increasingly widely used.

1 Principle and process of centralized insertion frame synchronization

1.1 Overall structure of centralized insertion frame

The centralized insertion method refers to a method of inserting a frame synchronization code sequence at the beginning of each frame of data. In this synchronous transmission mode, the transmitted data bits are organized into frames, each frame includes multiple data, and a frame synchronization code group (also called the frame flag word) is added to the head of the frame, denoted as U, with a length of M (unit: b), and the number of data bits in the frame is D. The receiving end searches the received bit stream. Once the flag word U is detected, it knows the beginning of a frame of data, and groups the data in the frame accordingly, thereby establishing a synchronous transmission mechanism. The data frame format of the centralized insertion method is shown in Figure 1.

Obviously, the frame synchronization code group must meet certain conditions: first, the synchronization code group is required to be as different from the data to be transmitted as possible to avoid mistaking the data for the synchronization code group; second, the frame synchronization code group is required to have a sharp single-peak autocorrelation characteristic to facilitate correct detection at the receiving end; the third requirement is that the length cannot be too long to avoid occupying too many channel resources. Currently, the commonly used frame synchronization code groups are mainly generalized Barker code sequences, and some systems also use m sequences with pseudo-random characteristics as synchronization code groups.

1.2 Several states of frame synchronization

According to the principle of frame synchronization search, there is obviously a possibility of false lock (also known as false alarm probability) in the frame synchronization search process, because the code sequence composed of data bits, or the code sequence of length M composed of part of the flag word and part of the data bits may also meet the detection conditions and be mistaken for U. Therefore, in order to improve the performance of the frame synchronization system (reduce the probability of false lock, and try to increase the stability of synchronization after locking), the engineering usually increases the complexity of the synchronization process to achieve the purpose of improving performance. Generally speaking, the frame synchronization process is divided into three states: search state, verification state and synchronization state, and its state transition diagram is shown in Figure 2.

Search state: At the start of data reception, or when an unsynchronized frame appears during frame verification, or when multiple consecutive frames are found to be unsynchronized during synchronization, the program enters the search state. In the search state, the program continuously searches for frame synchronization codes in the data stream. When a frame synchronization code is found in the received bit stream, it indicates that a synchronization frame header has been searched. At this time, a pulse signal is output and the system can enter the verification state.

Verification state: If the frame header found in the search state is confirmed to be correct through N consecutive frame synchronization codes, the system can immediately enter the synchronization state; otherwise, it means that there is false synchronization and it is necessary to return to the search state to search for the frame synchronization code again. The N-frame time from the first search for the frame synchronization header to entering the synchronization state is called the rear protection time.

Synchronous state: When the frame synchronization system is in the synchronous state, if there is no continuous M-frame data out of synchronization, it will remain in the synchronous state. Considering that the received data stream may be interfered by the outside world and there are errors, in the synchronous state, only when the synchronization code is lost for M consecutive frames will it enter the out-of-sync state and return to the search state. The time of this M frame is called the forward protection time.

2 VHDL Design and Simulation of Frame Synchronization System

2.1 Overall structural design

According to the requirements of the example, the frame synchronization code group length (LenCode), frame synchronization code group (FrameCode), error tolerance bit number (ErrorNum), frame length (Len-Frame), check state check frame number (CheckNum) and synchronization state check frame number (SyncNum) are all set in the form of constants to facilitate the modification of synchronization parameters in the VHDL program. The system data rate and clock frequency are 50 MHz.

According to the structure shown in Figure 2, it is easy to think of using the state machine design method to realize the synchronization system. Whether the state machine method or the schematic diagram method is used for VHDL program design, it can eventually be converted into the form of VHDL code. Obviously, directly using the form of writing VHDL code is more conducive to program modification and upgrade maintenance. Therefore, this article completely uses the code writing method for program design.

Figure 2 is a typical state transition diagram, and the transition conditions can be regarded as the signal interface between states. The entire frame synchronization system can be divided into a search state module (Search), a check state module (Check), and a synchronization state module (Sync). In addition to starting the search state after power-on, the search state also needs to be started when the check fails (a check frame in the CheckNum frame is not synchronized) or the synchronization state is lost (continuous SyncNum frames are not synchronized). Therefore, the start signals of the search state include the reset signal (rst), the check state re-search signal (Research_check), and the synchronization state re-search signal (Research_sync); the start signal of the check state comes only from the search state (search_over), that is, only when the frame synchronization code is searched can the check state be transferred to the check state. If the check passes, the check completion signal (check_over) is sent, and if the check fails, the re-search signal (Research_check) is sent; the start signal of the synchronization state comes only from the check state (check_over), and the synchronization state can be entered only after the check passes. After entering the synchronous state, the synchronous code group is continuously detected. When the re-lost lock is detected, Research_sync is sent to restart the search state. Figure 3 is the RTL schematic diagram of the top-level VHDL program file of the frame synchronization system after being synthesized using Synplify Pro.

2.2 VHDL Design and Simulation of Search Module

The external interface of the search module is shown in Figure 3. Among them, CLK_BitSync and Data_in are the bit synchronization clock signal and input data respectively; Data_out is the bit stream data after 2 clock cycles of delay. The delay processing of the input data is to compensate for the processing delay when search_over is generated, so that the pulse signal search_over is aligned with the last frame synchronization code.

To search for the frame synchronization code group in the input bit stream, you first need to send the input data to the shift register (Regdin), and then compare the data in Regdin with the frame synchronization code group. In the program, multiple start signals (rst, Research_check, Research_sync) are taken or used as asynchronous reset signals to start a search process. During the search process, a for loop is used to compare the register Regdin with the synchronization code group. By comparing bit by bit, every time 1 bit is found to be different, the count is increased by 1, and the Hamming distance between the two is calculated. After calculating the Hamming distance, it is determined whether it is greater than the error tolerance threshold ErrorNum. If it is greater than the error tolerance threshold, the search continues, otherwise the synchronization pulse search_over is output and the search stops.

Figure 4 is the Modelsim simulation waveform of the search module. Among them, the frame synchronization code length LenCode = 7, the frame synchronization code FrameCode = "1011000", and the error tolerance threshold ErrorNum = 1. It can be seen that after reset, the frame synchronization code group is first searched once; when Research_check is high, another search process is started, and "1001000 (ErrorNum = 1)" is searched in the bit stream, the error tolerance bit number is set to 1 at this time, so the same pulse search_over is output and the search process is stopped. Even if "1011001 (ErrorNum = 1)" appears in the subsequent bit stream, the synchronization pulse is still not output.

2.3 VHDL Design and Simulation of the Verification Module

To facilitate program writing, the verification module is mainly composed of the Check_Ce process and the Checking process. The Check_Ce process is used to detect the search_over signal. After detecting that the signal is at a high level, a high-level enable signal CheckCe with a length of CheckNum frame data is generated, and the position of the data and synchronization code group in each frame is identified by the counter Number. After the CheckCe and Number signals are generated, the Checking process only needs to verify the synchronization code group within the range where the CheckCe signal is at a high level. After the verification is completed, the check_over (consecutive CheckNum frames are synchronized) or research_check (one frame in the CheckNum frame is not synchronized) signal needs to generate a high-level pulse. The frame verification method is similar to the method of searching for synchronization code groups, that is, the Hamming distance is used to determine whether it is synchronized. If the verification state is divided into the Check_Ce process and the Checking process for separate implementation, the functional division of each process is simpler, and the programming implementation is relatively much easier.

Figure 5 is the Modelsim simulation waveform of the verification module. Among them, the frame length LenFrame=16, the number of verification frames CheckNum=2, the fault tolerance threshold ErrorNum=0, and the other parameters are the same as the search module. It is easy to see from the waveform that when search_over appears high for the first time, the two consecutive synchronization codes are "1011000 (ErrorNum=0)"; when search_over appears high for the second time, the first synchronization code is "1001000 (ErrorNum=1)", and the second synchronization code is "1011000 (ErrorNum=0)". Therefore, the first frame verification is successfully passed. After the verification is completed, check_over outputs a high level pulse, and research_check remains at a low level; the second verification fails. After the verification is completed, research_check outputs a high level pulse, and check_over remains at a low level.

2.4 VHDL Design and Simulation of Synchronous Module

In order to simplify the design, the synchronization state is divided into three processes, namely the counter process (Counter), the frame check process (FrameChecking) and the synchronization check process (SyncChecking). The Counter process is used to generate the count of the data position in the frame. When the check_over signal is detected to be high, the counting is restarted with the frame period (LenFrame); the FrameChecking process is used to generate the synchronization pulse at the start position of the frame, and the high-level pulse is aligned with the last 1 b of the synchronization code. The process first needs to check the synchronization code group. If the check passes, a high-level pulse FramePosition is generated at the synchronization code position. If the check fails, no high-level pulse is generated at the synchronization code position; the SyncChecking process determines whether the system is in a synchronous state by judging FramePosition, that is, it only needs to judge whether FramePosition continuously appears at a low level at the position of the synchronization code group. If SyncNum times of low level appear continuously, it is judged as a loss of lock, otherwise it continues to maintain the synchronization state.

Figure 6 is the Modelsim simulation waveform of the synchronization module. The synchronization state check frame number SyncNum=2, and other parameters are the same as the check state. It can be seen from the figure that when check_over is detected as a high level, the counter Number starts to count in a cycle with a frame length of LenFrame=16. When check_over appears at a high level, the following 4 consecutive groups of synchronization codes are "1011000(ErrorNum=0)", "1001000(ErrorNum=1)", "1001000(ErrorNum=1)", "1001000(ErrorNum=1)". Since the error tolerance threshold ErrorNum=0 is set at this time, the first frame synchronization code is checked and the synchronization pulse FramePosition is output. After that, there are 3 consecutive data frames that fail to pass the check. The high level state of the synchronization state signal State_Sync continues to maintain the length of 2 frames of data, and then stops the synchronization state, and outputs the out-of-step signal research_sync to start the search process.

3 FPGA Implementation and Simulation of Frame Synchronization System

The target device of this example is XC3S200-4FT200. After FPGA implementation, 484 lookup table resources (LUTs) are occupied (12%), and 1 global clock resource (GCLKs) is occupied (12%). The maximum system clock frequency (Maximum frequency) can reach 54.81 MHz. Figure 7 is the Modelsim simulation waveform of the frame synchronization system. Among them, the error tolerance threshold ErrorNum of each module is 0, and other synchronization parameters remain unchanged.

FIG7 actually performs a complete simulation test on the frame synchronization system's search, verification, verification failure, loss of synchronization, re-search, and re-synchronization processes.

4 Conclusion

This scheme is based on modular design ideas and uses VHDL language to design and implement the frame synchronization system, which is conducive to the relocation and maintenance of the program. The key to the scheme design is to understand the signal interface relationship and timing relationship between the modules. When designing the module, by further reasonably dividing the internal structure of the module, the program ideas can be better sorted out and the efficiency of the design scheme can be improved. Finally, the simulation test was carried out using Modelsim 6.0 software. The simulation results show that the synchronization system designed in this scheme works stably and meets the performance requirements.