Implementation of DDFS signal source based on CycloneII series FPGA

0 Introduction

In the field of electronic information, function generators (signal sources) are universal devices. With the rapid development of electronic information technology in recent years, the requirements for signal sources in various fields are constantly increasing. Not only are they required to have high frequency stability and accuracy, and to be convenient for frequency change, but they are also required to be able to generate arbitrary waveforms and output signals of different amplitudes. There are many methods to achieve frequency synthesis, but they can basically be summarized into two categories: direct frequency synthesis and indirect frequency synthesis. It is almost impossible to achieve the above requirements using traditional frequency synthesis technology. DDFS technology is a new type of direct frequency synthesis technology that has appeared since the 1970s. DDFS technology is proposed on the basis of the sampling theorem of signals. Starting from the concept of "phase", frequency synthesis can not only utilize the high frequency stability and high accuracy of crystal oscillation, but also the convenience of frequency change, fast conversion speed, and easy generation of arbitrary waveforms. Therefore, DDFS technology is the core technology of high-precision signal sources. At present, there are dedicated DDFS chips, such as AD9850 of AD Company in the United States, which can be used for the development of DDS signal sources, but their cost is relatively high. This design will use DDFS technology to design the signal source on FPGA, which greatly reduces the cost, and the design is flexible and convenient, and easy to expand various functions.

1 DDFS Technical Principle

The principle of DDFS technology is to store the sampled quantized data of various signals such as sine in ROM memory, read the data in ROM in sequence or at certain intervals under the control of the clock, and then realize frequency synthesis through D/A conversion chip and low-pass filter at the later stage. Its principle block diagram is shown in Figure 1. Its main components include: phase accumulator (which can also be understood as the read address generation unit of ROM storage unit), ROM table for sine signal sampled quantized data storage, D/A conversion and low-pass filter.

DDFS parameter calculation: The main parameters of DDFS include the number of sampling points of the sinusoidal signal, the highest output frequency fomax, the lowest output frequency fomax and the frequency resolution △fo. According to the DDFS principle, if all ROM storage data are read out in sequence under clock control, the output signal cycle is the longest Tomax=NTc, that is, the lowest output frequency is fomax; if only the sampling data of two points (∏／2 and 3∏／2) are read out, the output signal cycle is the shortest Tomin=2Tc, that is, the highest output frequency is fomax. Where Tc is the clock period. The corresponding calculation is as follows.

(1) The general formula of the output signal frequency is: fo = Sfc/2n, where 2n is the number of sampling points N, so n is the number of address bits of the ROM after sampling; where S is the step length, that is, one sampling point is taken for every S addresses;

(2) Output minimum frequency

(3) Output the highest frequency Although according to the Nyquist sampling theorem, sampling two points in one cycle can ensure that the signal's spectrum information is not lost, in order to reduce the distortion of the output signal after filtering, at least 8 points should be sampled in one cycle; therefore, it can be seen that the value range of S should be 1 to 2n-3;

(4) Frequency resolution △fo: △fo=fc/2n, consistent with the lowest frequency.

2 Parameter calculation of FPGA implementation of DDFS

This design makes full use of the on-chip resources of the Cyclone II series FPGA chip EP2C35 to implement a DDFS-based sinusoidal signal source. Since the available on-chip ROM unit of this chip is 483,840 bits of binary, the on-chip ROM resources can only store 215 (32768) 8-bit binary sampling points of data.

(1) ROM resource optimization: Since it is a sinusoidal signal, as long as the function value in the interval (0, n/2) is sampled, the corresponding function value in other intervals can be obtained based on its periodicity and symmetry. Therefore, although the on-chip resources can only store 215 (32768) 8-bit binary data, the symmetry of the sinusoidal signal can achieve 217-point sampling. Since the sinusoidal signal is negative between (n and 2n), the complement conversion is required when outputting the function value;

(2) Address bit length: The address of the ROM is a 15-bit binary number;

(3) Step length: The maximum step length should be 217/23=214, that is, the step length is a 14-bit binary number;

(4) Phase control word: Phase refers to which interval on (0, 2n) the data should belong to when reading. Since there are 4 different intervals, a 2-bit binary number can be used to identify it. Different phase intervals determine the reading direction of the address and whether the output function value is a complement operation.

(5) Generation of arbitrary waveforms: To generate arbitrary waveforms, the Fourier series decomposition expression of arbitrary waveforms such as rectangular pulses, triangle waves, sawtooth waves, etc. can be used to sum the first finite harmonics (such as the 10th) and store them in the specified RAM unit, and then read out the data in sequence to generate arbitrary signals. The data of the corresponding waveform can also be sampled, stored in ROM, and read in a certain step. Through the above analysis, on the basis of making full use of the on-chip storage unit, not expanding the external memory, and the address clock is 10 MHz, the frequency resolution can be obtained to be △f = 78 Hz, the maximum frequency of the output signal (at least 8 points are sampled in one cycle) is fomax = fc / 8 = 1.25 MHz; the minimum frequency of the output signal is fomin = Sfc / 2n | s = 1 = fc / 217 = 78 Hz. If the sampling points reach 232 or more, the frequency resolution can be 0.015 Hz, reaching the mHz level. It can be seen that the Cyclone II series chips can be used to design a signal source with excellent performance. [page]

3 FPGA Implementation of DDFS

According to the principle of DDFS, its FPGA design principle is shown in Figure 2. The control unit is composed of a finite state machine. Although the control of the entire system does not necessarily require the use of a finite state machine, the FPGA chip used does not support asynchronous ROM, that is, there is a delay of at least one clock cycle from the address latch entering the ROM unit to the data being read out from the ROM. Therefore, the state machine is used for control to achieve better output and clock synchronization. The control process is: the clock signal enters the control unit, which generates the input clock adrclk of the address generation unit. The address generation unit, driven by the clock adrclk, combines the input step signal Step to generate the address and the quadrant Phase corresponding to this address. This address is immediately input into the ROM unit after it is generated. After two clock cycles, the control unit reads the data corresponding to the input address from the ROM storage unit, and under the control of the clock, sends the quadrant value Phase generated previously to the complement conversion unit together with the ROM data. The complement conversion unit determines whether to perform complement conversion based on the value of Phase. If necessary, it performs complement operation and outputs the data. If not, it directly outputs the data. The specific design details of each module are given below.

(1) Control unit: The control unit is the core component of the entire system. It consists of a simple finite state machine. Its state transition diagram is shown in Figure 3.

(2) Address generation unit: The design idea is to calculate the number of points required for the four quadrants according to the input Step value, which means the number of points m required for a quadrant, and then count under the action of the clock. When the count value reaches m, it means that all points have been taken in a quadrant. At this time, the phase is incremented by 1 and the counting variable is reset to zero. Since the function value of sin at (0, π/2) changes from 0→1; the function value of (π/2, π) changes from 1→0; the function value of (π, 3π/2) changes from 0→-1; the function value of (3π/2, 2π) changes from -1→0. Therefore, in the (0, π/2) and (π, 3π/2) quadrants, the address value goes from 0→32767, and one data is read every other step. Of course, the latter data must be processed by the complement unit; and in the (π/2, π) and (3π/2, 2π) quadrants, the address value goes from 32767→0, and one data is read every other step. Similarly, the latter data must also be processed by the complement unit.

(3) ROM storage unit: The data of ROM storage unit can be obtained by calculation through Matlab and stored in the *.mif file format. When designing ROM, call this mif file as the initial data file of ROM.

(4) Complement code conversion unit: Determines whether to perform complement code conversion based on the quadrant where the current address is located. For example, when generating a sine signal, the sin function value in the (0, π) quadrant is positive, while the sin function value in the (π, 2π) quadrant is negative. Therefore, in the (π, 2π) quadrant, the output data needs to be converted into complement code. The complement code conversion unit is relatively simple and can be designed based on the principle of binary complement. [page]

4 Results Analysis

This design was completed on the QuartusII6.0 platform, and its simulation waveform is shown in Figure 4. The step length set in the simulation waveform is 1024 points. Due to the state machine for process control, the generated waveform is smoother and no glitches are generated. If the output signal frequency range is to be further increased, the clock signal should not be divided during the design process.

At the same time, the SigTapII tool of QuartusII can also be used to perform hardware verification on the designed program. After setting the corresponding steps, the corresponding output waveforms are shown in Figures 5 and 6. It can be seen that the generated low-frequency sine signal waveform is smooth, but there are certain glitches at higher frequencies, which can be filtered out by the low-pass filter circuit (such as Chebyshev low-pass filter network, etc.) at the later stage.

The logic unit used in this design only occupies 1% of the FPGA on-chip resources, the storage unit occupies 54%, and the I/O port occupies 13%. It can be seen that the main resources are the on-chip storage units. If one address bit is increased, the data volume will double, and the FPGA on-chip ROM will not be enough. Through the clock analysis of QuartusII6.0, the highest clock that this design can achieve is 149.41 MHz, and the clock of the address generation is 4 times the clock, so the highest clock of the address generation unit can reach 37.3525 MHz, and the corresponding output signal The highest frequency can reach 4.665 MHz, and the corresponding minimum frequency and frequency step are 284.976 Hz.

5 Conclusion

This design optimizes the DDFS design without expanding the ROM memory externally, making full use of the on-chip resources of the Cyclone II series FPGA, and the maximum frequency of the output sinusoidal signal can reach above 4 MHz. As long as a better solution is adopted for design, the sampling points can be 232 or more, the frequency resolution can be 0.015 Hz, reaching the mHz level, and the technical indicators such as the output signal frequency range and frequency resolution of the signal source can be further improved. The Cyclone II series chip can be used to design a signal source with excellent performance to meet the requirements of a practical signal source.