Design of Downsampling Filter for Sigma-Delta ADC in Electric Energy Metering Chip (Part 2)

3 Design of compensation filter

As can be seen from Figure 3, the amplitude-frequency characteristic curve of the CIC filter is not flat in the passband, and the signal is attenuated in the passband. In order to overcome this shortcoming, a compensation filter can be added, whose amplitude-frequency characteristic is just opposite to that of the CIC filter, to complete the compensation of the frequency response, thereby expanding the frequency characteristics of the system.

The basic principle of compensation is to make the attenuation of the signal in the passband zero. The amplitude response of the compensation filter is opposite to equation (4).

When R is large enough, the response of the compensation filter is close to the inverse SINC function, so the compensation filter is also called the inverse SINC filter.

The compensation filter can generally be simulated with the help of MATLAB, and then cascaded with the CIC filter to observe whether the total frequency response after compensation meets the system requirements, so as to obtain the parameters of the compensation filter. Figure 5 is the amplitude-frequency characteristic curve of the CIC filter in Figure 3 after adding compensation.

In Figure 3, the attenuation point is around 1kHz, and as can be seen from Figure 5, after adding the compensation filter, the attenuation point appears around 2.5kHz. Therefore, the compensation filter can well overcome the problem of amplitude attenuation in the passband due to the CIC filter.

The sampling frequency of the compensation filter is the frequency after the CIC filter is downsampled (FS/R). In order to avoid frequency aliasing, the maximum value of its cutoff frequency is half of the sampling frequency: FC = (FS/R)/2. In practical applications, in order to obtain a more ideal frequency characteristic, the cutoff frequency is generally set to one-fourth of the sampling frequency, that is, FC = (FS/R)/4.

4 Experimental data and conclusions

This design is for the energy metering chip. The sampling frequency of Sigma-Delta is 1792kHz, and the working clock of the digital circuit is 14kHz. The downsampling rate of the CIC filter is R = 64. According to experience, when the order of the CIC filter is one order higher than the order of the Sigma-Delta modulator, a better effect can be achieved. Therefore, this CIC filter is set to 3rd order and the delay factor is 1. The sampling frequency of the half-band filter is 28kHz. Through MATLAB simulation, the 6th order passband frequency is 2.5kHz, which can meet the system requirements. In the experiment, Verilog HDL language, HBF sampling symmetric structure and CSD coding are used, and the area and power consumption are synthesized under CSMC 0.18μm process, as shown in Table 1.

5 Conclusion

This design optimizes the Sigma-Delta downsampling filter according to the requirements of the energy metering chip. Since the single-stage CIC filter consumes a lot of power and the effect is not ideal when achieving high downsampling rates, this design performs hierarchical decimation for 128-fold downsampling. The front stage uses a CIC filter for 64-fold decimation, and the back stage uses a half-band filter for 2-fold decimation. In the implementation of HBF, a symmetrical structure and CSD encoding are used to reduce the number of multiplications in the operation process and the number of shift additions in the multiplication operation process, thereby reducing the power consumption of the circuit. Compared with the traditional method, after optimization, the circuit area is reduced by 8% and the power consumption is reduced by 15%.