Design of Downsampling Filter for Sigma-Delta ADC in Electric Energy Metering Chip (Part 1)

As the terminal metering instrument of smart grid, smart meter not only needs to accurately measure the user's electricity consumption information, but also needs various communication functions, such as RS485, infrared, power line carrier, etc., to realize automatic remote management. Therefore, smart meter plays a key role in the construction of the entire smart grid. And for the core of smart meter, the electrical measurement unit (EMU), higher requirements are also put forward. At present, the analog-to-digital conversion circuit of the metering chip basically adopts the Sigma-Delta type, and the downsampling filter is the core component of the Sigma-Delta ADC. Therefore, the research on the downsampling filter is of great significance.

In Sigma-Delta ADC, power consumption is mainly concentrated in the downsampling filter. The power consumption of the filter is mainly determined by the multiplier, so how to reduce the number of multipliers in the filter has become the research focus of downsampling design. HOGENAUE proposed a cascaded integrator comb filter (Cascaded Integrator Com, CIC). Since the CIC filter does not require multiplication operations, it greatly reduces the area and power consumption compared with the traditional direct downsampling through FIR filters. However, when the downsampling rate is large, the single-stage CIC filter cannot meet the requirements, and the power consumption is relatively large. The multi-stage sampling exchange theory and the multi-phase principle can reduce the number of multiplication operations. The difficulty of this method lies in the uncertainty of the multi-phase factor, and the filter structure and power consumption obtained by different multi-phase factors are different. The serial algorithm implements CIC to reduce power consumption, but the serial method is not suitable for parallel data processing in the metering chip. This paper proposes a cascade extraction method, which is not only simple in structure, but also easy to implement, and fully meets the needs of electric energy metering. The front stage is a CIC filter, and the back stage is an HBF filter to achieve 128 times extraction. Since HBF is only applicable to 2 The sampling rate of the front-stage CIC is 64 times. The non-zero coefficients of HBF are coded with signed CSD, which further reduces the power consumption of the circuit.

1 CIC filter principle and design

The basic structure of the CIC filter is shown in Figure 1, which consists of a cascade of an integral stage and a comb stage.

The sampling frequency of the integration stage is FS, and its transfer function is:

The downsampling multiple is R. Relative to the integration stage, the sampling frequency of the comb stage is FS / R, and its transfer function is:

Where M is the delay factor, which controls the frequency response of the comb stage. In the design, the value of M is generally 1 or 2.

Assuming the CIC filter has N order, the overall transfer function is:

The amplitude response is:

The advantage of CIC filter is that its structure is very regular, consisting of several cascaded integral stages and comb stages, and no internal multiplication operation is required. Therefore, it has been widely used in variable rate systems. However, with the increase of downsampling rate, the width of internal registers and power consumption will increase exponentially. The sampling frequency of the energy metering chip Sigma-Delta is 1792kHz, and the frequency of subsequent digital signal processing is 14kHz. Therefore, in this design, in order to achieve 128 times downsampling, a hierarchical decimation method is adopted. The overall framework of the downsampling filter is shown in Figure 2.

2 Design of Half-Band Filter

The second-stage decimation filter is used to attenuate the signal components and quantization noise components that are aliased in the baseband after passing through the first-stage comb filter. Since electric energy measurement has strict linear phase requirements for signals, FIR filters must be used. The half-band filter is a special linear phase filter whose even coefficients are all zero (the middle bit coefficient is 0.5), so the amount of computation required to achieve filtering is reduced by half compared to other linear phase filters of the same length, which will further reduce the chip area and reduce the power consumption of the circuit.

Considering the chip area and the frequency response of the system, the HBF is set to 6th order. Considering the high-order harmonics of the sinusoidal signal and the passband frequency of the CIC compensation filter, the passband frequency of the HBF is set to 2.5kHz.

Since the coefficient value of HBF is very small, insufficient quantization accuracy will affect the transmission characteristics of the system. The simulated coefficient uses Sfix48. En47 Bit, and the internal multiplier uses Sfix56. En55 Bit to meet the system requirements. Considering that the addition of complement fixed-point numbers may overflow, the adder is quantized to Sfix56. En54 Bit. Figure 4 is the HBF amplitude-frequency characteristic curve obtained by MATLAB simulation.

HBF operations include multiplication and addition, and multiplication consumes the most power. Traditional multiplication operations use the principle of shift addition, and the number of additions is equal to the number of 1s in the multiplier. Therefore, reducing the number of 1s in the multiplier can reduce the power consumption of the multiplication circuit. CSD coding meets this requirement. After CSD coding, the number of 1s in the multiplication coefficient is reduced to a minimum, thereby reducing the number of additions (or subtractions). CSD coding contains triple values ​​{1,0,-1}. The coding principle is to start from the least significant bit and replace all 1 sequences greater than 2 with 100...0(-1). For example, the multiplication coefficient b(3)= 0.28847028573567002 in the above HBF, and after quantization, b(3)= 48′h24EC98258D1E(Sfix48_En47), then the corresponding CSD coding b(3)= 0+00+0+000-0-00+0+0-00000+0+0-0-00+0-0+00+00+00-0 (“+” represents 1, and “-” represents negative 1).

x(n)*b(3) = – (x(n) < < 1) + x(n) < < 5 + x(n)< < 8 – (x(n) < < 10) + x(n) < < 12 + … + x(n)< < 40 + x(n) <44, Therefore, after CSD encoding, the multiplication operation of b (3) becomes only 10 additions and 7 subtractions, which reduces the number of operations compared to the traditional shift-add operation, thereby reducing the power consumption of HBF.