Design of digital converter test system based on FPGA

In the launch test of the aircraft, the telemetry system is often used to obtain the working state parameters and environmental data of each system inside it, which provides a basis for evaluating the performance of the aircraft and fault analysis. As an important device on the telemetry system missile, the digital converter has the main function of controlling various flight parameters on the receiving missile. The performance of the converter will directly affect the telemetry results, have a great impact on the test data test during the development and test of the aircraft, and will be related to the success or failure of the aircraft test and the improvement and improvement of the aircraft performance in the future. In the development process of the aircraft, multiple tests and assessments are very important. Making accurate, objective and reliable evaluation of the digital converter is a key link in its production process, and this link can only be completed by the converter test system. Programmable logic devices (FPGAs) have won more and more wide applications in modern test systems due to their advantages such as high speed, reconfigurability, flexible design, low development cost, rich I/O pins and internal resources. The test system designed in this paper with FPGA as the logic control center is mainly used to perform unit testing on digital converters, which plays a key role in its actual development and debugging process.

1 Overall system design

1.1 Technical indicators

(1) The test system can detect the various circuits and communication interfaces of the system itself before operation to determine whether the test system can work normally.

(2) Able to provide three DC operating voltages of 25V, 28V, and 31V for the digital converter, with a current driving capability greater than or equal to 1A.

(3) It can simulate the onboard equipment to generate computer word signals with an amplitude of 8~10V and corresponding shift pulse signals; generate 128 28V command signals; generate the required service signals (including frame synchronization signals and code synchronization signals); and receive computer word digital signals and command digital signals with a word length of 32 bits and an amplitude of 5V transmitted back through the converter, and display them on the host computer.

1.2 System structure and working principle

When designing the system, the idea of ​​modular design is adopted. Each functional module is designed according to the technical indicators, and the system test task is completed through the coordination between the modules. The overall structural block diagram of the system is shown in Figure 1. The whole system consists of a computer, a USB chip FT245, two FPGAs, an output power supply voltage control module, a computer word signal sending module, a service signal sending module, a computer word digital and instruction digital receiving module, and an instruction signal sending module. The modular design enables simple and rapid location and solution of problems during system debugging and hardware programming.

The test system uses the USB chip FT245 to realize the communication between the hardware circuit and the host computer, including the host computer sending control commands to the FPGA and uploading data.

The hardware circuit uses two FPGAs, XC3S200-208 and XC2S100-208, from XILINX as the logic control center of the system. XC3S200-208 is the master control chip, which mainly receives and judges the commands of the host computer, and then generates and sends computer word signals, receives computer word digital and instruction digital, frames, and uploads data to the host computer; XC2S100-208 is the slave control chip, which completes the transmission of 128 command signals; the two FPGAs use serial communication to send control commands to achieve communication. In addition, the host computer software can send reset or stop commands to the system, which can reduce the power consumption of the hardware and improve the working efficiency of the test system.

2. Functional realization of each module of the system

2.1 USB interface module implementation

USB has the characteristics of low cost, good versatility, simple connection, and hot plug support. Based on the actual transmission rate requirements of the system, the design uses the universal USB interface chip FT245BM to achieve communication with the host computer. The main function of FT245BM is to realize data serial/parallel bidirectional conversion under the action of internal logic, and its maximum transmission rate can reach 1M/s. FT245BM eliminates the need for complex firmware programming and driver programming, simplifies USB interface design, and saves design time for the system.

The specific circuit design of FT245BM is shown in Figure 2.

The 8-bit data lines D7~D0, read signal RD, write signal WR, transmit enable TXE, and receive data completion signal RXF of FT245BM are connected to FPGA to complete the communication between the two. The computer sends the control command signal to FT245BM through the effective cooperation of application program and dynamic link library, and FPGA receives the issued control command or sends the uploaded test data through the I/O port connected to it.

2.2 Output power supply voltage control module implementation

Since it is necessary to provide three working voltages of 25V, 28V, and 31V for the digital converter under test, three resistors with different resistance values ​​are connected to the output end of the power module to achieve switching of the three voltages. The control circuit is shown in Figure 3.

In the figure, VCON+ and VCON- are the input voltages of the power module, and the three sets of potentiometers R25, R26, and R27 are used to adjust the resistance. 25VCON and 31VCON are connected to the I/O of the FPGA respectively, and are the control signals given by the FPGA. The function of the transistor in the circuit is to increase the driving ability of the signal by using its current amplification. The FPGA determines the control command to achieve the control of the 3-level voltage. In addition, the default and reset output voltage of the system is 28V.

2.3 Implementation of computer word signal sending module

Since the amplitude of the computer word and shift pulse are required to be 8~10V, an operational amplifier circuit is used in the circuit to amplify the signal output by the FPGA to obtain the signal of the required amplitude. The computer word signal sending circuit is shown in Figure 4.

In order to meet the requirements of output signal accuracy and current driving capability, AD811 operational amplifier from AD company is used in this module to design the circuit. This operational amplifier is a high-speed operational amplifier, powered by dual power supplies, with a maximum conversion rate of 2500V/us, and has low current and electrical noise. The design adopts a voltage series negative feedback circuit with the same phase amplifier, and the output voltage is stable and the feedback effect is good. The grounding of R83 in the circuit is to minimize the voltage offset caused by the bias current, and its resistance is equal to the parallel resistance of R22 and R60, which is R22//R60=666Ω.

2.4 Implementation of service signal sending module

Computer word signals and command signals have corresponding service signals to meet the timing requirements. Generally, service signals refer to frame and code synchronization signals, which play the role of timing reference synchronization for the generation and reception of other signals. The circuit principle of the command service signal is shown in Figure 5. The computer word service signal has the same principle. According to the signal output requirements of the system, that is, the amplitude and current driving capability requirements of the frame and code synchronization signals, the NOT gate chip SN5405J is used as the driving circuit to meet the design requirements.

2.5 Implementation of digital receiving module The test system needs to receive the signal processed by the converter. The converter transmits it back to the test system in digital form, including computer digital and instruction digital. The receiving principle of the two is the same. The design uses optocoupler isolation to receive digital signals. The circuit schematic is shown in Figure 6.

The photocoupler uses TI's HCPL-2631, which has electrical insulation and anti-interference capabilities, and can effectively suppress various noise and spike pulse interference. Its two input terminals receive computer word digital and instruction digital respectively, and the diode connected to the photocoupler input terminal is used to prevent the internal diode from burning out due to signal rebound.

2.6 Implementation of command signal sending module

The command signal refers to a switch signal that is open or closed. All 128 command signals of this module are realized by optocoupler relays. According to the parameter requirements, AQY210 is selected as the device for controlling the switch. It is characterized by high voltage resistance, fast response speed and long service life. The principle of the single-channel command signal sending circuit is shown in Figure 7.

Since there are many command signal paths, if the FPGA I/O port output directly drives AQY210, it will inevitably increase the power consumption of the FPGA. Therefore, a transistor is used to amplify the current of the FPGA output signal to improve the driving ability of the control signal. This design uses NPN transistor 3DK103. 3order1 in the figure is the output signal of the FPGA. When it is '0', the transistor is cut off; when it is '1', the transistor is in current amplification. The current of 13mA flowing through the light-emitting tube of the photorelay is enough to turn on AQY210.

3. System FPGA Logic Implementation

The crystal oscillators used by the system master FPGA are 10M and 32.768M. The 10M crystal oscillator generates the system global clock signal and frame synchronization signal after the FPGA internal frequency division, and the 32.768M crystal oscillator generates the code synchronization signal; the slave FPGA also provides the system clock through the 10M crystal oscillator. After the system is powered on and stable, the FPGA will generate and send the frame synchronization signal (cycle is 25ms, pulse width is 25μs), and send the frame synchronization signal after the 25μs pulse signal. The signal generation is realized by the internal counter; and the computer word code synchronization signal has 8 pulse signals in a group, a total of 4 groups, and the instruction code synchronization signal has a total of 16 groups. In terms of timing, the first group of code synchronization signals of the computer word signal and the 16th group of code synchronization signals of the instruction signal are aligned. The converter will send a request pulse to the test system under the trigger of the rising edge of the frame synchronization signal. When the system receives the request pulse signal, it controls the FPGA to delay for 20ms, and generates a shift pulse signal and a computer word signal and sends them to the converter together. In terms of timing, the falling edge of the shift pulse signal is aligned with the middle of each bit of the computer word. The command signal is sent through the logic control of the slave FPGA. After the FPGA decodes the command signal of the host computer, it stores the command control signal in the internal register. The master FPGA sends the command in the register to the slave FPGA through serial communication. When sending, a set of data is 10 bits, including 1 start bit, 8 valid data bits and 1 stop bit. The FPGA deserializes the serial data and reframes it before outputting the command signal to the corresponding I/O of the FPGA. For digital reception, the digital signal is framed and stored in the internal register of the FPGA, and then the data is uploaded to the host computer through USB.

4 System Test Results

The reliability of the system design is ensured by repeated testing of the system. Figure 8 shows the waveform measured when the host computer sends all computer words as AAH. Channel 1 is the frame synchronization signal, channel 2 is the computer word request signal sent by the digital converter, channel 3 is the shift pulse signal, and channel 4 is the computer word signal sent by the system.

Figure 9 is the waveform of the system receiving computer digital measurement, channel 1 is the frame synchronization signal, channel 2 is the computer word request signal, channel 3 is the code synchronization signal, and channel 4 is the computer word digital signal.

Because the command signal is sent in parallel, the timing waveform is not involved. Figure 10 shows the waveform measured when the command signal is sent for 55H. In the figure, channel 1 is the frame synchronization signal, channel 2 is the code synchronization signal, and channel 3 is the command digital signal. It can be seen that the signal effect meets the design requirements and has high accuracy.

5 Conclusion

The test system makes full use of the powerful internal logic function of FPGA and the design of peripheral hardware circuits to achieve the system test function. Through the joint test of the test system and the digital converter, the output of each system is verified and the performance of the digital converter is tested in a balanced manner.