Theoretical analysis based on switched capacitor common-mode feedback

1 Introduction
Fully differential switched capacitor circuits have become a common circuit form due to their high output swing and suppression of common-mode noise such as power supply, as well as high precision of switched capacitor circuits [1,2,3,4,8]. The key and difficulty of fully differential circuit design is the design of common-mode feedback circuit [2]. The lack of a good common-mode feedback circuit will cause output common-mode voltage fluctuations, which will be converted into differential output through the asymmetry of the circuit, destroying the differential output signal. On the other hand, the deviation of the output common mode from the predetermined value will lead to limited differential output swing, resulting in clipping or bottoming distortion. At this time, the detected common-mode value deviates from the actual output common-mode value, and the return of the wrong control voltage further causes the common-mode voltage to deviate from the normal value, seriously affecting the circuit performance.

Until recently, there have been various papers analyzing switched capacitor common-mode feedback circuits [3,4,5,6], but various analyses still cannot provide a comprehensive and systematic theoretical analysis of switched capacitor common-mode feedback and have various defects. Since the working mechanism is somewhat different from that of continuous-time common-mode feedback circuits and is in a sampling system, it is difficult to analyze and simulate using continuous domain methods. Therefore, there has been a lack of sufficient analysis and design basis for a long time, resulting in a certain degree of blindness in the design.

This paper summarizes and proposes a new continuous-time equivalent common-mode and differential-mode analysis model for switched capacitor common-mode feedback, analyzes the common-mode (common-mode stability and loop establishment time) and differential-mode characteristics of the switched capacitor common-mode feedback circuit, and thus provides strong theoretical support for the design of switched capacitor common-mode feedback circuits.

2 Theoretical Analysis of Switched Capacitor Common-Mode Feedback Circuit

2.1 Basic Principle and Structure of Switched Capacitor Common-Mode Feedback Circuit

The common-mode feedback circuit is generally divided into two parts: the common-mode detection circuit and the comparison amplifier circuit. The basic principle is to detect the output common-mode voltage through the common-mode detection circuit, then input the comparison amplifier circuit and compare it with the pre-specified output common-mode reference voltage, amplify their difference and return it to the original circuit to correct the offset of the output common-mode voltage [2]. The common-mode feedback circuit can be divided into a continuous-time common-mode feedback circuit and a switched capacitor common-mode feedback circuit. The continuous-time common-mode feedback circuit is mainly used in continuous-time circuits, but it has the disadvantages of limiting the swing of the differential-mode output signal, increasing the differential-mode load, increasing the static power consumption and detecting the common-mode voltage nonlinearity. The switched capacitor common-mode feedback circuit has advantages in these aspects, but it is not suitable for continuous-time circuits because it will introduce clock coupling and discrete working states to cause glitches in the differential output signal. The switched capacitor common-mode feedback circuit has been successfully applied to data sampling systems, especially in fully differential switched capacitor circuits.

The continuous-time common-mode feedback circuit calibrates the output common-mode voltage offset continuously. However, the feedback control of the output common-mode voltage by the switched capacitor common-mode feedback circuit is discrete and is completed in half a clock cycle of each charge transfer. The calibration is also completed in a repeated half clock cycle. Therefore, the analysis method is different from that of the continuous-time common-mode feedback circuit. The circuit of the switched capacitor common-mode feedback is given in the paper [6] and has been used to this day. A switched capacitor integrator with a switched capacitor common-mode feedback circuit is shown in Figure 1. The left half of the circuit is the switched capacitor integrator circuit, and the right half of the circuit is the switched capacitor common-mode feedback circuit. The OTA is shown .

Figure 1. Switched capacitor integrator with switched capacitor common-mode feedback.

                                                               Figure 2 Amplifier prototype in switched capacitor circuit

2.2 Common-mode analysis of switched capacitor common-mode feedback circuit

The mechanism of action of switched capacitor common-mode feedback is different from that of other common-mode feedback. In essence, switched capacitor common-mode feedback controls the stability of the output common-mode voltage through each charge transfer, rather than directly detecting and controlling the output common-mode voltage like other continuous-time common-mode feedback. Therefore, in fact, the Vcm of switched capacitor common-mode feedback cannot be guaranteed to be stable at the specified voltage Vcmref in the end, and can only be estimated within a certain range.

Assuming that the analyzed circuit is completely symmetrical, the common-mode loop and differential-mode loop of the circuit will not interfere with each other under stable working conditions. Since the switched capacitor common-mode feedback circuit has two discrete states, it is impossible to perform common-mode equivalent analysis using the same method as continuous-time common-mode feedback. In traditional analysis, the switched capacitor common-mode feedback circuit is approximated using the same common-mode equivalent method and evaluation indicators (common-mode feedback loop unit gain bandwidth, loop gain, and phase margin) as continuous-time common-mode feedback. However, these indicators have different meanings in the switched capacitor common-mode feedback circuit.

                                                                  Figure 3 Common-mode analysis equivalent model of switched capacitor circuit

This paper proposes a new common-mode equivalent model of switched capacitor common-mode feedback, as shown in Figure 3. In the equivalent circuit of Figure 3, there are two common-mode amplifiers Acm1 and Acm2. Acm1 is composed of the common-mode path of the main amplifier, and Acm2 is composed of the common-mode feedback path. There are two loops around Acm2, each with its own establishment process. Loop 1 is composed of R2 and C2. Loop 2 is composed of Acm2 and C2. Among them, C1 is C9 and C10 in Figure 1, C2 is C7 and C8 in Figure 1, Cf is the integrator integration capacitor, and Ts is the sampling clock period. There are two situations, corresponding to different conclusions: (1) When the bandwidth of loop 2 is much larger than the bandwidth of loop 1, each charge transfer is complete. This is called loop 1 speed limitation. Under this condition, the establishment process of loop 1 determines the time for common mode stabilization. Its establishment time constant. If C1=C2, then it usually takes more than 5 cycles to recover from an output common-mode change. For the common-mode fluctuations that often occur with a period close to Ts, the switched capacitor common-mode feedback circuit has almost no stabilizing effect. However, it is not feasible to increase the output common-mode voltage stabilization speed by increasing the switched capacitor common-mode feedback sampling capacitor. This excessive capacitance will not only greatly increase the load of the differential-mode loop, but also cause huge differential-mode burrs. It can be seen that in this case, for the switched capacitor common-mode feedback circuit, no matter what sampling frequency the circuit operates at, the number of clock cycles required for its output common-mode voltage to reach a certain accuracy is constant, while the speed of the continuous-time common-mode feedback circuit to stabilize the output common-mode voltage has nothing to do with the sampling frequency of the circuit. The time constant corresponding to a continuous-time common-mode feedback circuit with a unit gain bandwidth of 100MHz is 10ns. Unlike the continuous-time common-mode feedback circuit, which increases the common-mode loop unit gain bandwidth to reduce the output common-mode voltage stabilization time, in this case, increasing the common-mode loop bandwidth (the loop composed of Acm2 and C2) in the switched capacitor common-mode feedback circuit cannot reduce the output common-mode voltage stabilization time, but can only reduce the time of each charge transfer, or the accuracy of establishment. (2) When the bandwidth of loop 1 is much larger than that of loop 2, each charge transfer is incomplete, the output common-mode voltage takes a long time to stabilize, and the output common-mode voltage is unstable. This is called loop 2 speed limitation. Assuming that the unit gain frequency of loop 2 is 100MHz, C1=C2, and the clock frequency is Ts, when 100M<5/Ts (assuming that 5 charges are fully transferred), that is, Ts<50ns, or the circuit operating frequency is higher than 20MHz, the switched capacitor common-mode feedback circuit cannot fully transfer the charge during each charge transfer between C1 and C2, so the output common-mode voltage stabilization speed will also decrease.

Therefore, the switched capacitor common-mode feedback is actually determined by the two loop settling times. When working at low speed (below 10MHz), the stabilization speed of the continuous-time common-mode feedback circuit will be higher than that of the switched capacitor common-mode feedback circuit. At this time, the stabilization speed of loop 1 of the switched capacitor common-mode feedback circuit is slower than that of loop 2, so the stabilization speed is determined by loop 1. Therefore, the stabilization speed of the continuous-time common-mode feedback circuit will be faster than that of the switched capacitor common-mode feedback circuit. When working at high speed (above 100MHz), the speed of the switched capacitor common-mode feedback circuit is limited by loop 2. The settling speed of this loop is equivalent to the continuous-time common-mode feedback time, but because there are two loops and two settling processes, in general, it will be slower than the continuous-time common-mode feedback circuit. Therefore, in terms of common-mode stabilization speed, the continuous-time common-mode feedback circuit will be better, especially in low-frequency circuits.

Thus, the equivalent model of switched capacitor common-mode feedback and continuous-time common-mode feedback is obtained, so the continuous-time common-mode feedback theory can be used to analyze the switched capacitor common-mode feedback circuit. It can be seen that k3

Assuming that the loop time constants of the two loops are equal, both are Ts (sampling period), and the corresponding continuous-time common-mode feedback loop time constant is also Ts, then the switched capacitor circuit is equivalent to the continuous-time loop establishment time constant

 In Figure 3, the two loops of the common-mode feedback have a common path (C2), so the common point can be disconnected to determine the stability of the two loops. If both loops are stable, the common-mode feedback loop is stable [5]. Loop 1 must be stable, so only loop 2 needs to be stable. The stability of this loop can be detected by measuring its phase margin.

In the switched capacitor application environment, there is another common-mode amplifier path Acm1 that also works on the output common-mode voltage. Reduce the common-mode gain of the main amplifier circuit to reduce the impact of input common-mode changes on the output common-mode, so that the output common-mode voltage fluctuation of the previous stage will not affect the output common-mode voltage of the next stage. At the same time, the loop should ensure sufficient phase margin.

2.3 Analysis of the load impact of the switched capacitor common-mode feedback circuit on the differential-mode loop

The load effect of the switched capacitor common-mode feedback circuit on the differential loop can be analyzed using the model in Figure 4.

                                                      Figure 4 Equivalent model for analyzing the impact of switched capacitor common-mode feedback on differential-mode load

R1 represents the equivalent resistance of the sampling capacitor of the switched capacitor filter, C1 is the feedback capacitor of the fully differential amplifier, CL is the differential mode load capacitor, C' is the common mode feedback capacitor C7 and C8 connected across the output and control ends, and R' is the equivalent resistance of the sampling capacitors C9 and C10 of the switched capacitor feedback circuit. The increase in the load of the differential mode circuit by the switched capacitor common mode feedback circuit lies in the size of the common mode feedback capacitor and the common mode feedback sampling capacitor. The smaller the absolute value of these two capacitors, the smaller the impact on the differential mode loop, which is also one of the requirements for the design of the common mode feedback circuit. In contrast, the stability of the common mode feedback loop has little to do with the absolute value of the common mode feedback capacitor. Increasing the value of the common mode feedback sampling capacitor will increase the speed of establishing loop 1 in the common mode feedback loop, but it will also increase the load of the differential mode feedback loop, reduce the circuit processing speed, and may cause distortion. Reducing the size of the common mode feedback capacitor can reduce the load effect on the differential mode feedback loop, while having little effect on the common mode loop.

4 Conclusion

This paper analyzes the common-mode characteristics and the impact on the differential-mode loop in detail through the common-mode and differential-mode equivalent continuous-time models of the switched capacitor common-mode feedback circuit for the first time. Through this analysis, the switched capacitor common-mode feedback can be analyzed and designed more effectively.

Innovation of this paper: This paper analyzes the common-mode characteristics and the impact on the differential-mode loop in detail through the DC, common-mode and differential-mode equivalent models of the switched capacitor common-mode feedback circuit for the first time. Through this analysis, the switched capacitor common-mode feedback can be analyzed and designed more effectively.

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Author profile: Wu Yuchun (1982-), male (Han nationality) ), born in Sichuan, is a master's student at the Institute of Microelectronics, Tsinghua University, and is engaged in the research of large-scale mixed-signal integrated
circuits . High-performance integrated circuit design and implementation.
Correspondence address: 16#116, Institute of Microelectronics, Tsinghua University, Beijing 100084