Interface Circuit Design of ATM Data Acquisition Card Using PCI9052

1. Introduction

With the development of CPU, the original industrial bus standard ISA/EISA bus has been unable to keep up with the pace of the times. PCI bus, as an advanced high-performance 32/64-bit local bus, can support multiple sets of peripheral devices at the same time and is not restricted by processor and clock frequency. It is fully compatible with existing ISA/EISA/MAC and other expansion buses. It is very suitable for high-speed peripherals such as display cards, network cards, and multi-serial port cards. It has replaced the original ISA bus's dominant position and become the mainstream bus for microcomputer systems.

2. PCI Bus Overview

The PCI bus is not attached to a specific processor. In addition to being applicable to Intel chips, it is also applicable to other types of processor chips and can implement P&P, that is, when the system is powered on, the BIOS can automatically detect the machine configuration and allocate interrupt request signals and memory buffers to each peripheral device. There are two methods for developing PCI interface devices. One method is to use programmable logic chips, which is more flexible and users can develop chips suitable for specific functions according to their needs. Another commonly used method is to use dedicated interface chips. The dedicated chip can realize the functions of the complete PCI master module and target module, converting the complex PCI bus interface into a relatively simple user interface. We only need to design the converted bus interface. PCI9052 is a commonly used bus interface chip. This article describes in detail the interface circuit design using PCI9052. The main innovation lies in the configuration space of the PCI9052 register and the processing of high-speed signal lines in PCB wiring.

3. Working principle of PCI9052

PCI9052 is a hybrid high-performance PCI bus target (slave) mode interface chip launched by PLX for expansion adapter cards. The chip can be interconnected with a variety of local buses and supports burst transmission rates of up to 132Mb/s on the PCI bus. As a target interface chip, PCI9052 can only be used as a slave device, but its functions are unique.

3.1 Initialization and Reset
During the power-on process, the internal registers of PCI9052 are reset by the RST# signal of PCI BUS, and a response signal RETRY is given, and the LRESET# signal is output on the LOCAL BUS. It also checks whether the serial EEPROM exists. If the EEPROM is installed and its first 16 bits are not FFFFH, PCI9052 uses the values ​​in the EEPROM to configure the registers on the chip, otherwise the default values ​​are used. The master device on the PCI bus can also reset the PCI9052 through software (setting the corresponding bit in the NCTRL register) and give the LRESET# signal. After this reset, the master device can only access the configuration registers of PCI9052, but not the LOCAL BUS, until the master device clears the bit reset by software.

3.2 On-chip register access

To provide maximum flexibility in interface design, PCI9052 provides two types of on-chip registers: PCI configuration registers and local configuration registers. Both can be accessed via the PCI bus and serial EEPROM. Access to the serial EEPROM can also be disabled by setting registers CNTRL[13]~CNTRL[12].

3.3 Direct Data Transmission Mode

PCI9052 supports PCI master devices to directly access devices on the LOCAL BUS. The data transmission methods are divided into memory-mapped burst transmission and I/O-mapped single transmission, and the PCI base address register sets its appropriate position in the PCI memory and I/O space. The local mapping register also allows the PCI address space to be converted to the local address space.

3.4 Generation of PCI Interrupts

The PCI specification defines four interrupt signals. Taking INTA# as an example, to generate the PCI interrupt INTA#, you must first set the 6th bit (PCI interrupt enable bit) of the INTCST register to 1; if you need to generate an interrupt in software mode, you only need to set the 7th bit (software interrupt bit) of INTCST to 1.

4. Using PCI9052 for bus interface design

                                                                       Figure 1 ATM data acquisition card structure diagram

ATM (Asynchronous Transfer Mode) is not only suitable for high-speed information transmission and support for quality of service (QOS), but also has the ability to integrate multiple services, as well as dynamic bandwidth allocation and connection management capabilities and compatibility with existing technologies. The ATM system has a bright future. The ATM data acquisition card developed and designed by the author's research institute uses PCI9052 as the interface chip, selects a long card that supports 5V32 bits, selects 93AA46 for EEPROM, and selects non-multiplexing mode for 9052. The above figure is its structure diagram.

The ATM data acquisition card receives STM-1 cells transmitted by optical fiber through the optical port, converts STM-1 cells into ATM cells through the physical layer PM5384, FPGA interprets ATM cells into signals required by users, and PCI9052 controls the transmission of signals between the ATM data acquisition card and the PC.

4.1 Register Configuration

The PCI bus supports three physical spaces: memory address space, I/O address space, and configuration space. Configuration space is a space unique to PCI, and all PCI devices must provide configuration space. The serial EEPROM stores important configuration information of PCI9052. Its content is very important and directly related to whether the entire board can work properly, so it needs to be paid special attention to. When the system is powered on, after the PCI RST reset, PCI9052 first detects whether the EEPROM exists. If it is detected that the first word of the EEPROM is not FFFFH, PCI9052 will read the contents of the EEPROM in sequence to initialize the internal registers. PCIBIOS allocates resources according to the contents of the configuration register, thereby realizing the plug-and-play feature of the PCI bus. The configuration of the PCI configuration register is shown in Table 1.

PCI9052 also includes local configuration registers to configure the base address, address space range, address space descriptor, and chip select signal of the PCI device. Users can configure the local configuration registers of PCI9052 in EEPROM, or use the system to assign default values ​​to the device. The configuration of the local configuration registers is not necessary, and the default configuration can be used in general.

4.2 PCB Layout and Wiring

4.2.1 PCI card power requirements

When designing the circuit diagram, the PCI specification must be followed. The capacitor between the power layer and the ground layer can provide decoupling for the power pins on the connector. All 3.3V pins and unused 5V pins need to be coupled to ground using the following method:
(1) Each power pin must have a decoupling capacitor with a capacitance of at least 0.01µf.
(2) The trace length from the root of the pin to the capacitor pad should not exceed 0.25 in and the trace width should be at least 0.02 in.
The maximum power consumption allowed on the PCI expansion board is 25W, which refers to the sum of the power consumption from the four power lines. The maximum power consumption can also be set to 15W or 7.5W, which is determined by the PRSNT1# and PRSNT2# pins on the connector.

4.2.2 Trace length

The trace length from the expansion card connector to the pins of the PCI components is subject to the following restrictions:
(1) The maximum trace length of all interface signals is 1.5 in.
(2) The trace length of the clock CLK signal is 2.5 in and can only be connected to one load.

4.2.3 Layout and Routing

The PCI interface card uses a four-layer board structure. When wiring the power layer, the "split power layer" technology is used, which divides the power layer into two power layers, 5V and 3.3V. In order to prevent the signal integrity problem of high-speed signals when crossing the power layer and the impedance discontinuity caused by the AC loop of the signal line blocked at the break, try not to arrange high-speed signals on two power planes. They should all be arranged on the 3.3V plane or above the 5V plane. If some signals have to cross two areas, they can be placed on the other side of the spanner so that they are routed above the ground plane. If some signals cannot be prevented from crossing the crack between the two power layer planes by any means, the two power layer planes should be coupled together with capacitors. A 0.01µF high-speed capacitor is used for every four crossed lines, and the position of the capacitor is no more than 0.25 in. from the crossing point.

4.3 Driver Development

There are three common development environments for developing WDM drivers, Windows DDK, DriverStudio and Windriver. Considering their advantages and disadvantages, we use DriverStudio to complete the development of PCI9052 driver. PCI devices have two characteristics that make its driver different from "standard" or existing device drivers.

The first feature is that PCI devices are relocatable. That is, the address space of the device is not fixed by hardware. The PCI device driver and other configuration software should use the mapping information in the device configuration space to decide where to map the device. This can be implemented in the routine OnStartDivce.

The second characteristic is that PCI interrupts are shared. Because in system implementation, it is very likely that various devices will be connected to an interrupt line, which requires the PCI device driver to support shared interrupts. In DivceStudio, the Kinterrupt class is used to implement interrupt processing, call member functions to initialize interrupts, and control the connection and disconnection between one interrupt service program and another. For the framework generated by DriveWizard, it calls InitializeAndConnect() on an interrupt object in OnStartDevice(KIrpI) to complete initialization and connection. In order to realize the sharing of PCI interrupts, the interrupt service program must quickly determine whether it is an interrupt from its own board. If so, it returns TRUE, otherwise it returns FALSE. For work that requires a lot of operations, the interrupt service program will call a delayed call function below the DIRLQ level to complete the processing at DISPATCH-LEVEL.

4.4 Verification

Open the device through Creatfile, use DeviceIOcontrol to send the IOCTL control command and the buffer address to the driver, and the driver uses DMA to pass the data reorganized by FPGA plus a header information (VPI, VCI, message type, etc.) to the upper test program. It has been verified that the received data information is consistent with the data information sent by the sender and the operation is stable.

5. Conclusion

This article discusses the design process and issues that need to be paid attention to when using PCI9052 as the interface circuit of ATM data acquisition card, and makes an in-depth discussion on register configuration and high-speed signal layout and wiring. It has been verified that the interface circuit designed with PCI9052 has a simple circuit design and can meet the rate requirements of ATM data acquisition card.

References:

1 PCI Local Bus Specification ,Revision 2.1, June 1, 1995
2 PCI9052 DataBook 2.0 September ,2001
3 Li Guishan, Qi Dehu, PCI Local Bus Developer's Guide Xidian University Press
4 Liu Hui translated PCI System Architecture [M], Beijing Electronic Industry Press
5 Wu Qiuming, He Weixing. Serial communication between PC and multiple microcontrollers based on RS-484 bus. Microcomputer Information, 2005, 8-1: 2-3.
Innovation: Register configuration of PCI9052 interface circuit design and layout of high-speed signals.

About the Author:

Zhang Lei (1983-), male, from Dezhou, Shandong, is a master's student at the School of Communication
, Chongqing University of Posts and Telecommunications. His main research direction is embedded technology research. Qiu Shaofeng (1971-), male, from Bengbu, Anhui, is an associate professor and master's supervisor at Chongqing University of Posts and Telecommunications. His main research direction is broadband access network.
Contact address: Communication and Test Technology Laboratory, Chongqing University of Posts and Telecommunications, Postal Code: 400065