256-level grayscale LED dot matrix screen display principle and circuit design based on FPGA

Introduction256
-level grayscale LED dot matrix screens are increasingly showing their broad application prospects in many fields. This paper proposes a new control method, namely, bit-by-bit time-sharing control.With the emergence of large-scale programmable logic devices, high-speed and complex control by pure hardware has become possible.

Working principle of bit-by-bit time-sharing
lighting The so-called bit-by-bit time-sharing lighting is to extract one bit of data from a byte of data in turn, and light up the corresponding pixel in 8 times. The duty cycle of each lighting time and off time corresponding to each bit is different. If the lighting time increases from low to high, there will be 256 combinations of the synthesized lighting time. Define the lighting time plus the off time as a time unit, set as T. Table 1 lists the time allocation of lighting and off for each bit.
If the data bit "1" is defined as valid (lit) and "0" is invalid (extinguished), then Table 2 lists the different lighting times when the data is from 00H to FFH. It can be seen from Table 2 that for every increase of 1 in data, the lighting time increases by T/128. According to the principle that the lighting time and brightness are basically linear, the lighting time from 0~255T/128 corresponds to 256 levels of brightness. Of course, this brightness is a cumulative effect over time. If lighting the same data point corresponding to all pixels of an LED dot matrix screen is called one field, then 8 fields are required to display 8 bits of data, which is called the "8-field principle".
Theoretically, 8 fields can display 256 levels of grayscale. However, it can be seen from Table 2 that even when the data is FFH, it is only lit for 255T/128 time in 8T time. The off time can be close to 6T, and the lighting time is only about 25% of the total time. Therefore, although the 8-field principle can also achieve 256-level grayscale display, the brightness loss is too large. In order to improve the brightness, the "19-field principle" can be adopted, that is, 8 bits of data are displayed in 19 fields, of which the D7 bit data is displayed continuously for 8 fields, and the D6 bit is displayed continuously for 4 fields, and they decrease in sequence. Table 3 lists the lighting and off time of each bit.
From Table 3, the total lighting time of data from 00H to FFH can be derived, as shown in Table 4. In 19T time, the maximum lighting time can reach nearly 16T, accounting for 84.21% of the total time, which is much larger than the 25% of the "8-field principle". Every time the data increases by 1, the lighting time increases by T/16, which is greater than T/128 of the "8-field principle". Therefore, the contrast of the "19-field principle" is more obvious than that of the "8-field principle", and the image is clearly layered and has strong expressiveness.

Circuit Design
256-level grayscale LED dot matrix screen usually has the function of remote synchronous real-time display of computer video signals. The circuits involved include: digital video signal acquisition, digital signal format conversion and nonlinear correction, remote transmission and reception, grayscale display control circuit, LED dot matrix display circuit, etc. This article focuses on the design of "grayscale display control circuit", and the control object is the red and green dual-primary color LED dot matrix screen and 1/16 scanning display circuit as an example. The internal circuit of FPGA is shown in Figure 1.
Because the controlled object is a 1/16 scanning display circuit, only one data signal is needed for every 16 lines of the display screen. DRout1 and DGout1 are the red and green primary color output signals of the first 16 lines; DRout2 and DGout2 are the red and green primary color output signals of the second 16 lines. And so on.
The binary encoding of Ha, Hb, Hc, and Hd defines which line of the 16 lines the current data output should be. The CP signal is the synchronous shift pulse of the data serial output. The LE signal is a latch pulse after a row of serial data output is completed. Each time LE is valid, the binary code states of Ha, Hb, Hc, and Hd increase by 1. EA is a grayscale control signal, and its width is the lighting time of the LED in one time unit T. Of course, different data bits have different widths, which are determined by Table 3. One time unit T is the transmission time of a row of serial data, that is, the cycle of the LE signal, and its size depends on the number of pixels in the screen width and the frequency of the CP signal.
DRin1~8 and DGin1~8 are red and green data input signals, corresponding to the first 16-row dot matrix area to the eighth 16-row dot matrix area, respectively. Cpin is a synchronization pulse, one pulse corresponds to one bit of data, and 8 pulses correspond to 8-bit data input of one pixel. The H signal is a row synchronization pulse. When a row of data input is completed, the H signal is valid once. V is a frame synchronization pulse. When a frame (16 rows) of data input is completed, the V signal is valid once. The above signals are all signals provided by the previous system.
There are two groups of high-speed static RAM (not shown) connected to the outside of FPGA. DRA1~8 and DGA1~8 are the red and green data lines of RAM group A, and DRB1~8 and DGB1~8 are the red and green data lines of RAM group B. /WRA and /RDA are the read and write control signals of group A, and /WRB and /RDB are the read and write control signals of group B. AA0~16 are the address lines of group A, and AB0~16 are the address lines of group B. The purpose of using two groups of RAM is to ensure that the read and write operations of RAM can be performed simultaneously. When writing RAM (A), read RAM (B); when writing RAM (B), read RAM (A). The write/read switching of the two is controlled by the frame signal V. Each time V is valid, a switch is performed.
Cpin is the write pulse provided by the previous system, and it is also used as the counting pulse of the write address generation circuit. The counting address range is A0~A16, a total of 128K bytes, of which A0~A2 is the grayscale bit data address (determines which bit of the 8 bits to access). A3~A12 is the pixel address in the X direction, and A13~A16 is the pixel address in the Y direction, that is, the row address. When the H signal arrives, A0~A12 is cleared, and the address of A13~A16 is increased by 1. When the V signal arrives, A0~A12 and A13~A16 are all cleared. The above addresses are used as the write address of RAM.
CLK is the count pulse of the read address generation circuit (provided by the external circuit), and the count address range is also A0~A16, a total of 128K bytes, of which A0~A9 is the pixel address in the X direction, and A10~A13 is the pixel address in the Y direction, that is, the row address. A14~A16 is the grayscale bit data address. The above addresses are used as the read address of RAM. The change rules of these addresses should comply with the change rules of the address requirements of the "19-field principle", that is: A0~A9 is cleared after counting up, and a row signal, namely the LE signal, is generated. The LE signal is used as the counting pulse of A10~A13. A10~A13 is cleared after counting to generate a field signal. The field signal is used as the counting pulse of A14~A16. However, A14~A16 is not a simple binary count. Its rules are shown in Table 5. In order to correctly read the data written to the RAM, the generated read address should be connected to the RAM according to the method shown in Table 6.
The function of the read-write control circuit is to provide read-write control signals to the two groups of RAM. The logical relationship is shown in Table 7. The function of the data input/output circuit is to switch the transmission direction of the data, as shown in Table 8. The function of
the frame switching circuit is to generate the switching signal S required by the above circuit. The implementation method is that the logical state of S flips once every time the frame synchronization pulse V is valid. The frame switching circuit ensures that the two groups of RAM continuously perform read-write conversion with the V signal. The
grayscale signal generation circuit generates the EA signal required by the controlled object, which changes with the state of the read addresses A14, A15, and A16. The logical relationship is shown in Table 9.
According to the principle that the frame period Tp=20ms and one frame=19 fields, the following calculation results can be obtained: Field period Tv=Tp/19=1.05ms; Line period T=Tv/16=66ms; Output shift pulse period Tcp=T/1024=64ns; Output shift pulse frequency fcp=1/Tcp=15.6MHz. CLK signal frequency fclk=fcp=15.6MHz; In actual application, the CLK clock signal frequency is selected as 16MHz.
In the MAX PLUSII10.0 environment, the above circuit design is completed using graphics and hardware description language.

FPGA selection and simulation results
As shown in Figure 1, the FPGA must provide 113 I/O pins, and the internal resources and operating frequency must meet the circuit design requirements. The ACEX1K series EP1K10QC208-3 chip of Altera is used. This FPGA chip has high speed, low price, 114 I/O pins, 576 logic macro units, and is compatible with the TTL level of the input and output circuits. Simulation result report: The pin utilization rate reaches 99%, and the internal logic unit utilization rate reaches 85%, achieving the purpose of fully utilizing resources and improving cost performance. ■