LED display screen control solution based on FPGA

As an important medium for modern information release, LED (Light Emitting Diode) large screens are receiving great attention from all walks of life, especially the business and advertising sectors, and are widely used in the fields of industry, transportation, commerce, advertising, finance, sports competitions, simulated military exercises, electronic landscapes, etc. With the advancement of technology, full-color LED display screens (RGB three primary colors) are gradually becoming popular.

This solution uses Actel's FPGA to control the color LED screen, which greatly enhances the reliability of the system, and the low-cost single chip greatly reduces the cost of the system.

1. Overview

(1) Functional Overview

The selection of FPGA to realize the control of LED full-color screen mainly considers the system performance requirements, system upgrade needs and system design costs. The high requirements of modern society for information display effects and the increase in video data volume have posed challenges to the display controller, as shown in Figure 1. The LED full-color screen implemented in this article mainly realizes the following functions:

● Ensure that the full-color LED display does not display color distortion;

● Able to achieve 256 levels of grayscale;

● Able to correctly display text, pictures, animations and other information;

● Can receive DVI data stream output from PC and display it in real time.

Figure 1 LED display application example

(2) System block diagram

The controller mainly completes the control and display of the LED scanning board, including color control, grayscale control, data reconstruction, storage form, scanning method selection, etc. The functional block diagram of the controller is shown in Figure 2.

Figure 2 LED display controller functional block diagram

2. Introduction of each functional module

The main difficulty in implementing the controller lies in its grayscale control. Using the visual effect of the human eye, we know that as long as the refresh frequency is high enough to prevent the LED device from flickering, the longer the LED device is on, the brighter the display will be. For this reason, we will use the duty cycle waveform of the LED device on and off time to control the grayscale level. Below we will introduce the grayscale control in 8-field scanning and 19-field scanning modes respectively.

(1) 8-field scanning module

The 8-field scanning method is proposed for serial drive LED display screens. For the most common 8-bit width display data, we display it 8 times. The first time, the 0th bit of the 8-bit data is displayed on the LED screen, and the second time, the 1st bit of the 8-bit data is displayed on the LED screen. Repeat this operation until all 8 bits of data are displayed on the LED screen. As long as the scanning frequency is high enough, the effects of the 8 displays are superimposed to obtain a complete data display effect. We call the lighting of the same data point corresponding to all the pixels of an LED dot matrix screen a field. 8 fields are required to display 8 bits of data. This method is called "8-field scanning".

In the "8-field scanning" mode, the lighting time corresponding to each data bit is shown as follows. Let the time for scanning a row be T. As can be seen from Table 1, the lighting efficiency of this mode is relatively low.

Table 1 Data corresponding to lighting time

Based on the above 8-field scanning method, as shown in Figure 3, we correspond each of the 8-field scanning to a fixed duty cycle signal to control the on and off of the LED device. From the analysis, we can see that the weight of each bit of 8-bit data: 1, 2, 4, 8, 16, 32, 64, 128, is the duty cycle factor corresponding to each field, and the duty cycle of each field is: 1/256, 2/256, 4/256, 8/256, 16/256, 32/256, 64/256, 128/256. The complete duty cycle value of a pixel is equal to the sum of the product of each bit of 0/1 data and the corresponding weight. Calculation shows that this ratio is exactly from 00 to FF, which constitutes 256 gray levels.

Figure 3 Data bit grayscale weight

(2) 19-field scanning module

Based on the "8-field scanning" introduced in the previous section, we know that the serious disadvantage of 8-field scanning is the low lighting efficiency. Therefore, as a functional improvement of the controller, we designed the "19-field scanning" method, which continues the idea of ​​serial drive and only makes some changes in the data bit reading.

As shown in Figure 4, it can be seen that the principle of the 19-field design is to display the high bit of the data several times in succession to increase the display brightness of the data. The 19-field scan of the lower 5 bits of data is the same as the 8-field scan, but the 5th bit is read twice in succession, the 6th bit is read 4 times in succession, and the 7th bit is read 8 times in succession.

Figure 4 Bit address of 8-field scan and 19-field scan

At the same time, it should be noted that when changing the number of times a data bit is displayed, the duty cycle value of its color should not be changed. Calculation proves that the number of times each data bit is read in the 19-field scanning mode is more reasonable. The grayscale control of 19-field scanning is based on the same principle as that of 8-field grayscale control. In the 19-field scanning mode, although an 8-bit data is displayed 19 times in total, the data bit is still scanned from the 0th bit to the 7th bit, so as long as the corresponding duty cycle signal is loaded to the fixed data bit to control its grayscale display, it can meet the requirements.

(3) Controller clock tree design

Because the controller in this article combines two scanning modes, and the working frequency of each scanning mode is different, the entire controller involves more working frequencies, that is, there are many cross-clock domain working phenomena, as shown in Figure 5, here we make full use of the FPGA's timing logic resources. Actel FPGA has a very rich clock network. In addition to the global clock network, it also has a segmented wiring structure inside, which can make the FPGA have up to 252 clocks inside.

Figure 5 System clock domain distribution diagram

In addition, since the data that the controller needs to process is relatively large, according to the design concept of FPGA, ping-pong operation is used to store data to improve the data processing speed. In terms of data source, the controller can display static images stored internally or external input data. When processing data transmitted from the previous system, the data interface problem is involved. According to the interface processing design concept of FPGA, FIFO is used as the data interface to achieve data synchronization.

3. Market Application

LED displays are already very common in information dissemination situations and are widely used in industries such as industry, transportation, commerce, advertising, finance, sports competitions, simulated military exercises, and electronic landscapes, as shown in Figure 6. As the demand for quality of life becomes higher and higher, LED displays can also be used for interior decoration, exhibition hall displays, etc. In the future, the application of LED displays will become more and more extensive, and the application of Actel's FPGA can provide the best solution for LED controllers.

Figure 6 LED display application example