DSP Parallel Boot Loading Method Based on Flash Memory

TMS320VC5409 is the first generation of high-performance, low-cost, low-power digital signal processor (DSP) launched by TI. Compared with the popular TMS320C5409, the performance is improved by 60% and the power efficiency is improved by 50%. Its application objects are mostly embedded systems that require offline operation, such as set-top boxes (STBs), personal digital assistants (PDAs) and digital wireless communications. Flash memory (FLASH MEMORY) is a memory that can be electrically erased online and does not lose information after power failure. Compared with EPROM, FLASH has a higher performance-price ratio, and is small in size, low in power consumption, fast in erase and write speed, and more convenient to use. Therefore, using FLASH to store programs and fixed data is a better choice. AMD's Am29LV400B FLASH can be directly connected to DSP.

1 Main features and programming methods of Am29LV400B

Am29AL400B is a new 256K×16-bit product launched by AMD, with the following main features:

(1) Support single power supply operation, which can be divided into two power supply modes: full load voltage supply (2.7V ~ 3.6V) and voltage range adjustable (3.0V ~ 3.6V). The full load voltage supply mode is mainly used in battery-powered applications, while the voltage range adjustable power supply mode directly interfaces with 3.3V high-performance DSPs, simplifying the system power supply requirements.

(2) The fastest access speed is up to 55ns, CMOS process, and has a write/erase life of 100,000 times.

(3) Low power consumption (200nA auto-sleep current, 200nA standby current, 7mA read current, 15mA program/erase current).

(4) Flexible block structure supports full chip erase and block erase. The whole chip is divided into 11 blocks (1 block of 8K words, 2 blocks of 4K words, 1 block of 16K words, 7 blocks of 32K words).

(5) Block protection function, which has a hardware protection mechanism to prevent programming or erasing of any segment.

(6) Compatible with JEDEC standards, pin distribution and command set are compatible with single-power FLASH, and has superior protection against accidental programming.

(7) Data query bit and data toggle bit can be used to detect the status of program/erase operation through software methods.

(8) Ready/Busy# pin, which can detect the status of program/erase operation through hardware methods.

(9) It has the function of erase suspend/erase resume. During the erase suspend operation, it supports reading and writing blocks that are not in the erase state.

(10) The built-in erase/program algorithm can automatically perform erase and program operations on the entire chip or certain blocks.

The command definitions for the Am29LV400B programming and erasing algorithms are shown in Table 1.

Table 1 Am29LV400B command definition

In the table, RA is the memory address to be read; RD is the data read from the memory address RA; SA is the segment address to be erased; PA is the memory address to be written; PD is the data to be written at the address PA. According to the command in the table, the "burn" and "erase" programs of FLASH can be compiled (implemented by mixed programming of C language and assembly language). According to the needs, we have compiled the programs of "burning" single words and "burning" multiple words.

2 Hardware circuit composition

The DSP storage area hardware interface circuit is shown in Figure 1. It mainly consists of five parts: DSP processor-TMS320VC5409, system logic control circuit (implemented by CPLD-EPM7128), flash memory FLASH-Am29LV400B (256K words of FLASH are used to store application programs and initialization data), program memory SRAM1-IDT71V416S12PH (capacity is 256K words), data memory SRAM2-IDT71V016S12PH (capacity is 64K words). The logic control circuit mainly consists of three modules: FLASH page selection control module, read/write control module, program space/data space/FLASH switching control module. In the figure, the output FMSEL of CPLD is the chip select pin of FLASH; PMSEL is the chip select pin of program space; DMSEL is the chip select pin of data space.

FLASH is divided into 8 pages, each page is 32K, and the FLASH page turning function is realized through the FLASH page selection control module (Page0~Paeg2) in the CPLD. In order to realize FLASH boot loading, the first 32K of FLASH physical space is mapped to the data space 0x8000h~0xFFFFh of TMS320VC5409, that is, the data space 0x8000h~0xFFFFh of TMS320VC5409 is the first 32K space of FLASH. In order to focus on the boot loading process of FLASH, this article only discusses the use of the program storage space on the DSP chip and the first 32K words of FLASH.

The TMS320VC5409 chip has two boot modes: on-chip boot mode and off-chip execution mode. The on-chip boot mode is to use the boot program in the on-chip ROM to load the program from the outside to the program memory for execution. Since the speed of FLASH is low and difficult to match with DSP, this article adopts the on-chip boot mode.

The bootloader program solidified in the mask ROM on the TMS320VC5409 chip is used to boot the user program from the outside to the high-speed RAM at power-on reset to ensure its full-speed operation. The on-chip boot methods provided by the TMS320VC4509 include: organic port HPI method, 8-bit or 16-bit parallel EPROM method, 8-bit or 16-bit parallel I/O method, and 8-bit or 16-bit serial port method. The TMS320VC5409 on-chip bootloader source program can be downloaded from the TI network, and readers can analyze it by themselves. The following is an explanation of the parallel boot method process selected in this article through the boot process block diagram shown in Figure 2.

After power-on reset, TMS320VC5409 detects its MP/MC pin. If MP/MC = "0", DSP starts to execute the on-chip boot loader from 0xFF80h. After entering the boot program, if there is an INT2 request interrupt, it enters the HPI boot mode; if there is an INT3 request interrupt, it enters the EEPROM serial port boot mode; otherwise, it enters the parallel boot mode. The detailed boot process is shown in Figure 3.

The first half of the on-chip parallel boot mode is the I/O space parallel boot mode. We do not use this mode. The program continues to run until an address data is read from the data space 0xFFFFh address. This data is the entry address of the user boot table. At this time, the on-chip boot program starts to execute the user boot table in FLASH. If the first word of the boot table is 0x10AA, it means it is a 16-bit parallel boot mode.

4 Storage format of bootable table in FLASH

In order to realize DSP power-on self-booting, the data of FLASH must be "burned" according to the format of the bootstrap table. The function of the bootstrap table is: when the DSP runs this table, first load the following user program code into the corresponding user address area in the DSP on-chip program space according to the user start address in the front part of the bootstrap table (since the FLASH and DSP time do not match, the SWWR and BSCR registers must be set), and then start running the program at the corresponding address in the program space according to the program entry address in the bootstrap table. Table 2 is the code structure of 16-bit parallel bootstrap (the bootstrap table can contain several program code segments if space allows, for ease of explanation, only one program code segment is described here).

Table 2 Code structure of parallel bootstrap table

The following example illustrates how to use the hex500 command to generate a binary data bootstrap table.

(1) A user program is written named myblink.C. After successful compilation and linking, the output file is named myblink.out; the starting address of the program space is 0x1400h, and the entry address of the program execution is 0x144Fh. Use the hex500 tool to generate binary data with the file name myblink.hex. Add the following conditions after the hex500 command:

mybilink.out ; .out file to be converted

-a ; Generate ASCII code

-e 0x144Fh ; Start of program execution in program space

address

-boot ; Convert to bootstrap table format

-bootorg PARALLEL ; parallel format

-byte ; allocate addresses by bytes

-memwidth 16 ; system memory word width is 16 bits

-romwidth 16 ; ROM physical width is 16 bits

-swwsr 0x7FFFh ;SWWSR sets the software wait cycle

-bscr 0xF800h; BSCR sets the segment switch control register value 0xF800

-o myblink.hex ；output binary data file name

(2) The data in the generated binary data file myblink.hex is:

0x10AA 0x7FFF 0xF800 0x0000 0x144F 0x00D1 0x0000 0x1400 …(user program code) … 0x0000;

The first 8 data explanations are:

0x10AAh: 16-bit parallel addressing format;

0x7FFFh: The initial value of SWWSR is 0x7FFFh, because the running speed of FLASH is slower than that of DSP, so it waits for 7 cycles;

0xF8000h: BSCR initial value is 0xF800h;

0x0000h: XPC of the bootstrap program entry = 0;

0x144Fh: address of bootstrap table program entry = 0x144Fh;

0x00D1h: bootstrap table program length = 0xD1h;

0x0000h: bootstrap table starting address XPC=0;

0x1400h: Start address of boot table = 0x1400h.

(3) Write a data conversion program to convert the binary data file myblink.hex into the array header file myblink.h. In the CCS environment, the FLASH "burning" main program contains this header file. After compilation and linking, it is downloaded to the DSP through the emulator. When the DSP is run, the user program is "burned" into the FLASH.

The actual application is: "burn" data 0x9000h (the starting address of the bootstrap table stored in FLASH) in the data space address 0xFFFFh (that is, the FLASH space 0xFFFFh), and start "burning" the user bootstrap table data, that is, the array data in myblink.h, at the FLASH address 0x9000h.

The operation of DSP is as follows: according to the boot loading process described in Section 3, after a series of settings, DSP addresses to the data space address 0xFFFFh, obtains the starting address 0x9000h of the boot table, the PC pointer points to 0x9000h, executes the data of the boot table, and according to the information written in the boot table, loads the subsequent program into the program space starting address 0x1400h (XPC=0) (at this time, the data starting from 0x1400h of the program space is viewed through the emulator, which is consistent with the data of the myblink.out file downloaded by the emulator). Then, the PC pointer of DSP points to the program entry address 0x144Fh (XPC=0) to start executing the user program, thus completing the process of DSP using FLASH to implement 16-bit parallel boot loading.