Freescale HCS12(x) memory map explanation (1).

For people who use MCU, it is not necessary to understand the mechanism and connection of HCS12(x) memory map. Because if you do not systematically study courses such as operating system and compiler theory, it is indeed difficult. In addition, for MCUs such as DG128 XS128, the default memory allocation method is sufficient. In this sense, it seems unnecessary to understand the memory map.
 

However, have you ever had a situation where you don't have enough RAM? Have you ever wanted to define variables in FLASH ROM? Have you ever defined variables in non-paged area to improve addressing efficiency? Have you ever failed to write to EEPROM?
Freescale's memory is very flexible. Improving efficiency through address mapping is a common practice of chip manufacturers (of course, first of all, the CPU must have this addressing and memory mapping conversion mechanism). However, looking at the HCS12(x) memory map, it is really the limit. In my previous words, it is to use limited resources to obtain unlimited benefits. Look at DG128, 64K logical space, after mapping, RAM EEPROM FALSH ROM, can fully play a role, and it is also convenient to expand FLASH. XS128 is more advanced, with a dedicated MMC to manage HCS12(x) memory map.
 

I have a general understanding of the HCS12(x) memory map of these two chips, so I would like to share my understanding and opinions on this. If there are any errors, please feel free to point them out.
 

First, let’s talk about 6 concepts.
 

1 memory map address mapping, do not understand it as memory mapping, memory is RAM.
 

2 Why is mapping necessary? Because the addressing of the CPU is based on the physical address operation, but after the RESET of the microcontroller, there is only a relative address. I understand the relative address as a piece by piece, not a continuous one. As the name implies, the relative address is relative. Before mapping, the CPU cannot find it, nor can it use the data of the relative address. Here is an explanation from Baidu: In order to ensure that the CPU can correctly access the storage unit when executing instructions, the logical address in the user program needs to be converted into a physical address that is directly addressed by the machine at runtime. This process is called address mapping.
 

3 RAM, I won’t say much about this, it is used to store variables and stacks, it is high-speed and will be lost when power is off.
 

4 EEPROM, this is a special kind of FLASH. It is generally used to save a small amount of data and will not be lost when the power is off. FLASH is also non-volatile, and SD card is a kind of FLASH. The difference between EEPROM and ordinary FLASH lies in the byte operation when reading and writing. I basically have no experience with this because it is a very low-level thing.
 

5 FLASH and ROM. In HCS12(X), it is recommended to understand FLASH and ROM as equivalent. Your program is stored here. There is also a const variable and interrupt vector in it. There may be a misunderstanding about ROM, which can only be read but not written, one-time, which is good. However, there is a premise that it should be a controllable ROM.
 

6 There is also an important register space, which is used to store I/O addresses and microcontroller programmable registers. It is defined by the manufacturer and can be seen in the header file. For example, extern volatile PORTABSTR _PORTAB @(REG_BASE + 0x00000000) is a typical register space mapping.
  

I understand memory map as three things: one is mapping management, one is paging mechanism, and one is addressing. Mapping management is the relationship between logical address and physical address after the microcontroller is reset. The paging mechanism is mainly due to the limited addressing capability of 16 bits, which requires paging. In addition, it can gain more advantages in virtual memory management. As for the CPU addressing problem, I won't go into it in depth.
  

This time we take DG128 as an example. XS128 is a little more complicated. If you understand DG128, XS128 will not be a big problem.
  

Let's talk about mapping management first: In DG128, mapping is achieved by setting INITRG, INITRM, and INITEE. For specific settings, see DS. By default: register space is mapped to 0X0000 to 0x03FF, which has the highest priority. RAM space is mapped to 0x0400-0X1FFF. See, there are only 7K in reality, which means that only 7K RAM can be used. However, DG128's RAM has 8K logical space. Therefore, you can change INITRG, INITRM, and INITEE to remap to increase the actual available space of RAM. How to change depends on the need. WJ will say a word here, you can see how PE is changed. And FLASH maps 3, there are two non-paged addresses 0x4000-0x7FFF and 0xC000-0xFEFF. There is also a paged address, and this paged address has 6 pages. Six pages occupy one paging window and one logical space. How can these six pages work together and allow the CPU to find them?

This is the content of the paging management mechanism. The 6 pages are:
     

      PAGE_38 = READ_ONLY 0x388000 TO 0x38BFFF;
      PAGE_39 = READ_ONLY 0x398000 TO 0x39BFFF;
      PAGE_3A = READ_ONLY 0x3A8000 TO 0x3ABFFF;
      PAGE_3B = READ_ONLY 0x3B8000 TO 0x3BBFFF;
      PAGE_3C = READ_ONLY 0x3C8000 TO 0x3CBFFF;
      PAGE_3D = READ_ONLY 0x3D8000 TO 0x3DBFFF;
  

As mentioned above, you can create a new DG128 project and look at the PRM file.
  

Let's look at the paging management mechanism: In DG128, only the FLASH space can be paged, while in XS128, there are too many things to page. In DG128, FLASH paging is done through the PPAGE register. PPAGE is a 5-bit register, and the CPU12 core specification states that each page can only have 16KB. Therefore, the FLASH addressing space of DG128 is 2^5*16KB=512KB.