A single-cell lithium battery protection IC design

A low-power single-cell lithium-ion battery protection circuit is designed. This protection circuit not only provides overcharge, over-discharge, and discharge overcurrent protection for lithium-ion batteries, but also provides charging abnormality protection, zero-volt battery charging prohibition and other functions. It is implemented using 1. 0μm dual-well CMOS technology.

2 Analysis of the functional principle of lithium battery protection IC

The schematic diagram of the lithium battery protection circuit is shown in Figure 1. A charger or load is added between the E+ and E- terminals. The circuit works as follows:

Figure 1 Lithium battery protection schematic

Normal state: When the battery voltage is higher than the overdischarge detection voltage and lower than the overcharge detection voltage, and the VM pin voltage is higher than the charger detection voltage and lower than the overcurrent detection voltage, both the charge control FET2 and the discharge control FET1 are turned on.

At this time, free charging and discharging can be performed. This state is called the normal state.

Overcharge protection: During the charging process, when the battery voltage is higher than the overcharge detection voltage and this state lasts until the overcharge detection delay time, the control circuit outputs a low level, turns off the charging control FET2, and prohibits charging.

Over-discharge protection: During the discharge process, when the battery voltage is lower than the over-discharge detection voltage and this state lasts until the over-discharge detection delay time, the control circuit outputs a low level, turns off the discharge control FET1, and prohibits discharge.

Overcurrent protection: Overcurrent protection includes primary overcurrent protection, secondary overcurrent protection, and short circuit protection. When the discharge current is too large, the VM terminal voltage rises and exceeds the overcurrent detection voltage, and the state lasts longer than the overcurrent detection delay time, the control circuit outputs a low level, turns off the discharge control FET1, and the discharge is prohibited. During the discharge process, the VM terminal voltage is the voltage drop across the two FETs in the on state (see Figure 1), that is, VVM = I ×2RFET. In the formula, I is the current passing through the FET, that is, the discharge current, and RFET is the on-state resistance of the FET.

Abnormal charging protection: If the battery current is too large during charging, the VM voltage will drop. When it is lower than a certain set value and this state lasts longer than the overcharge detection delay time, the control circuit turns off the charging control FET2 and stops charging. When the VM voltage rises above the set value again, the charging control FET1 is turned on and the abnormal charging protection is released.

Zero volt battery charging prohibited: When the battery is not used for a long time, it will discharge itself and the battery voltage will drop, even to zero volts. Some lithium batteries are not suitable for recharging after being fully discharged due to their characteristics. When the battery voltage is lower than a certain set value, the gate of the charging control FET2 is fixed at a low potential and charging is prohibited. Charging is allowed only when the battery voltage itself is above the zero volt battery charging prohibited voltage.

3 Circuit Design

As shown in Figure 2, the lithium battery protection circuit is mainly composed of a reference source, a comparator, a logic control circuit, and some additional functional blocks. The reference voltage used by the comparator detection must be provided by a reference source circuit. Under normal working conditions, this reference source must be high-precision and low-power to meet the chip requirements and be able to work normally when the power supply voltage is as low as 2.2V.

Figure 2 Internal structure of lithium battery protection circuit

Figure 3 is a bandgap reference source that meets this requirement. In this circuit, P4, P5, P6, P7, N3, N4, and N6 form a two-stage op amp as the feedback of the reference source, and the bias voltage of the op amp is provided by the reference source, which simplifies the circuit and layout and reduces the extra power consumption. By adjusting the size of the MOS tube, the op amp has a higher gain and a lower offset voltage. The reference source adopts the form of cascaded diodes, and the emitter areas of Q1 and Q2 are equal, and the emitter areas of Q3 and Q4 are equal. In order to reduce power consumption, the area of ​​Q3 is twice that of Q2. The cascaded diode form can effectively reduce the impact of the op amp offset on the accuracy of the output reference voltage.

The detection voltage used in the protection circuit is generally low, for example, the primary overcurrent detection voltage is about 0.15V, and the secondary overcurrent detection voltage is about 0.6V, but the general bandgap reference circuit can only output a voltage of about 1.2V. The introduction of resistor R5 is to solve this problem by dividing the output reference voltage again. The calculation formula of the output reference voltage is given below:

Figure 3 Reference source circuit structure

It can be seen from formula (4) that 2 ln ( IS3 / IS2 ) VT is significantly less affected by the offset voltage VOS than ln ( IS3 / IS2 ) VT, that is, the use of cascaded diodes reduces the influence of the reference voltage on the operational amplifier offset.

The factor R5 / (R4 + R5) is generated in the formula. By adjusting the resistance values ​​of R4 and R5, a reference voltage less than 1.2V can be obtained.

In Figure 1, N1, N2, P1, P2, P3, and C1 are used as the startup circuit, and the active resistors P1 and P2 play a current limiting role. N5 and P13 are switch tubes. When the protection circuit is in a dormant state, the circuit must stop working to minimize power consumption. At this time, the internal control circuit makes L1 low-potential, and the P13 tube is turned on, so that the bias point VB IAS rises to a high potential, and the P4, P7, P8, P9, P10, P11, and P12 tubes are turned off, and the N5 tube is turned off, cutting off the branch formed by P13 and N6. The circuit stops working and the current is almost zero. After simulation, the reference circuit can work normally at a voltage of 2.2V.

The following introduces the additional functions of this lithium battery protection IC, including charging abnormality detection function and zero-volt battery charging prohibition function, as shown in Figure 4.

Figure 4 Additional function circuit structure

When the lithium battery is connected to the charger for charging, the VM terminal is equivalent to the negative terminal of the charger (see Figure 1), generating a pulse voltage of about -4V, and the N1 tube is turned on instantly. At the same time, the OUT1 terminal also generates a pulse voltage of -4V. When the logic circuit detects the negative pulse voltage at the OUTI terminal, it controls L2 to a high potential through logic control, turning on the N3 tube. Because the gate of the P1 tube is grounded, when VDD is greater than the threshold voltage of the P1 tube, the P1 tube is turned on, the D1 point is a high potential, the N2 tube is turned on, the D2 point is a low potential, the P4 tube is turned on, the CO is a high potential, and the charging control FET2 is turned on to allow charging, that is, the charger detection is completed.

When the lithium battery voltage drops below the PMOS threshold due to self-discharge, the P1 tube is cut off, D1 is low, the N2 tube is cut off, the node D2 cannot drop to the VM terminal voltage, the P4 tube is cut off, the CO terminal is low, the charging control FET2 is turned off, and charging is prohibited, which is the zero-volt battery charging prohibition function. During the charging process, the VM terminal potential is - I ×2RFET (see Figure 1), I is the charging current, and RFET is the FET on-resistance. When the current is too large, the VM terminal potential drops below the negative NMOS threshold, the N5 tube is turned on, the D3 potential drops, the P6 tube is turned on, and the output OUT2 is high. After this state lasts for a period of time, the control logic determines that the state is valid, so that L2 is low, the N3 tube is cut off, the P3 tube is turned on, and the D2 is high, so that the CO terminal is low, the charging control FET2 is turned off, and charging stops, which is the charging abnormality detection function.

4 Simulation timing diagram

Figure 5 is the HSPICE simulation timing diagram of overcharge and overdischarge detection. It can be seen that when the comparator detects that the battery is overcharged, the overcharge detection point is 4.25V, and the state is maintained for a time that reaches the overcharge detection delay time, which is about 1.2 seconds, CO outputs a low level, turns off the charging FET2, and stops charging. When the battery is detected to be over-discharged, the over-discharge detection point is 2.25V, and the state is maintained for a time that reaches the over-discharge detection delay time of about 150 milliseconds, DO outputs a low level, turns off the discharge FET1, and stops discharging. Other functions such as discharge overcurrent detection fully meet the requirements after HSP ICE simulation, and are not listed here one by one.

Figure 5 Overcharge and overdischarge detection simulation timing diagram

5 Conclusion

The designed single-cell lithium battery protection IC consumes 3.3uA of current in normal working state and 0.15uA in sleep state. The overcharge detection accuracy is ±25mV. It can operate at a temperature of -40°C~85°C. The product performance fully meets the requirements.