Video matrix switching device based on video switching chip AD8112

Introduction

Video surveillance systems have been developed for just over 20 years, from the earliest analog surveillance to the popular digital surveillance in the past few years, and then to the current network video surveillance, which has undergone earth-shaking changes. Video surveillance systems have been increasingly widely used in ports, factories, banks, airports, transportation, etc. In large-scale monitoring systems, due to the large number of monitoring points, there are also many video images that need to be monitored, so a large number of cameras are required. The ratio of the number of monitors in the monitoring center to the number of on-site cameras is generally 1:5 to 1:10, so the video matrix switching device plays a very important role in the entire monitoring system.

At present, the video matrix switching systems used in China are generally small in scale, and most of them control the switching of the video matrix through a keyboard connected to the RS232 serial port, which makes remote control very cumbersome. This paper uses NXP's ARM7-based microcontroller LPC2378 and ADI's video matrix switching chip ADS112 to form a video matrix switching device, realizing a video matrix with 64 video inputs and 8 video outputs with an Ethernet interface. The monitoring center can send video switching control commands and pan-tilt operation control commands to LPC2378 through network transmission, and then LPC2378 processes the command data sent by the host computer according to the protocol to control the video matrix and the camera pan-tilt. In this way, the operator can use a visual host computer to switch the video through Ethernet. With the support of the host application software, the system has the function of automatic and cyclic switching of videos, and can operate the pan-tilt of each camera remotely through network communication.

1 Features of LPC2378

LPC2378 includes 10/100M Ethernet MAC, USB 2.0 full-speed interface, 4 UARTs, 2 CAN channels, 1 SPI interface, 2 synchronous serial ports (SSP), 3 I2C interfaces, 1 I2S interface, MiniBus, 4 general-purpose timers, 10-bit A/D converter, RTC, watchdog and 104 general-purpose I/O pins. The features of LPC2378 are as follows:

①ARM7TDMI-S processor, which can run at operating frequencies up to 72 MHz.

② Up to 512 KB of on-chip Flash program memory with in-system programming (ISP) and in-application programming (IAP) capabilities. The time to erase a single Flash sector or the entire chip is 400 ms, and the time to program 256 bytes is 1 ms. The Flash program memory is on the ARM local bus and can be accessed by the CPU with high performance.

③There is up to 32 KB of SRAM on the ARM local bus, which allows high-performance CPU access.

④16 KB static RAM for Ethernet interface, which can also be used as general-purpose SRAM.

⑤8 KB static RAM for USB interface, which can also be used as general-purpose SRAM.

⑥ Two AHB systems can perform Ethernet DMA, USB DMA, and execute programs from the on-chip Flash simultaneously without any competition. The bus bridge allows Ethernet DMA to access other AHB subsystems.

⑦ The external memory controller supports static devices such as Flash and SRAM. The 8-bit data/16-bit address parallel bus is only available in LPC2378.

⑧Advanced vector interrupt controller, supporting up to 32 vector interrupts.

⑨ The general-purpose AHB DMA controller (GPDMA) can be shared with the SSP serial interface, I2S port and SD/MMC card port, and can also be used for memory-to-memory transfers.

The Ethernet controller integrated in LPC2378 uses the RMII interface to communicate with the peripheral circuit PHY chip (such as DM9161A), making it easy to implement Ethernet communication functions.

2 AD8112 Features

ADS112 is a 16-input, 8-output video matrix switching chip from ADI. All inputs and outputs have cache. ADS112 has a switch matrix consisting of 128 independent electronic switches, which can realize 16 video inputs and 8 video outputs. The matrix switch is 100% non-blocking. By writing control series words in serial or parallel programming, any input and any output connection can be enabled. Each output can be connected to any of the 16 analog input signals. The functional structure block diagram of AD8112 is shown in Figure 1.

The output of AD8112 is equipped with a high-speed amplifier, and the compensation of the amplifier is automatically optimized to the maximum bandwidth of each gain selection. Each output can be enabled by the 5th bit of the control series word. When disabled, the output pin can be regarded as a 4 kΩ resistor, and multiple disabled output pins can be connected together. When powered on or asynchronously reset, all output pins will be initialized to a disabled state to avoid conflicts in the output of large-scale video matrices.

The digital interface of AD8112 consists of the following pins: DATA IN, DATA OUT, CLK, LIPDATE, CE, SER/PAR, 194~D0, A2~A0 and RESET. Among them, DATA IN is the serial data input terminal, DATA OUT is the serial data output terminal, CLK is the serial input clock, UPDATE is the data latch terminal, CE is the chip select terminal, SER/PAR is the programming mode control terminal, D4~D0 and A2~A0 are parallel data and address loading terminals, and RESET is the reset terminal.

AD8112 provides two programming modes: serial programming and parallel programming, which are selected by the high and low levels of the SER/PAR pin. When SER/PAR=0, the serial programming mode is selected: the data input by DATA IN is loaded on the falling edge of CLK, the data is latched on the falling edge of UPDATE, and the matrix is ​​programmed; DATA OUT is shifted and output through the 80-bit matrix mode register. When SER/PAR=1, the parallel programming mode is selected: the data input by D4~D0 in parallel and the address input by A2~A0 in parallel are loaded on the falling edge of CLK; the data is latched on the falling edge of UPDATE, and the matrix is ​​programmed.

The AD8112 serial programming control timing diagram is shown in Figure 2.

In serial programming mode, the control word input from DATA IN of AD8112 is shown in Figure 3. The first 40 bits of the control word correspond to one video output for every 5 bits, arranged in order from OUTPUT7 to OUTPUT0. D4 controls the output enable, D4=1 enables the output, and D4=0 disables the output; D3~D0 selects the video input terminals INPUT15~INPUT0. Since 40 bits of the 80-bit shift register with 5-bit parallel loading in AD8112 are not connected internally, the last 40 bits of the control word are written as 0.

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For a large matrix consisting of N AD8112 chips, these chips can be programmed by a series of N × 80-bit serial data streams. The AD8112 parallel programming control timing diagram is shown in Figure 4.

3 Composition of 128×16 video matrix

This design uses 4 AD8112 chips to form a video switching matrix, realizing video switching of 64 video inputs and 8 video outputs. The corresponding pins of each AD8112 output are connected in parallel. When a certain numbered pin of one AD8112 is enabled, the corresponding pins of other chips will be set to the disabled state to ensure that there is no conflict in the output when the video is switched. When the power is just turned on, all output pins are initialized to the disabled state to prevent output conflicts. The connection method is shown in Figure 5.

The connection between ADS112 and LPC2378 in this video matrix is ​​shown in Figure 6. The DATA IN pin of the first ADS112 is connected to the P2.15 port on the LPC2378 to obtain the control command, and the control word is sent to the four AD8112s through serial shifting. The DATA OUT of each AD8112 is connected to the DATA IN of the adjacent chip. The P2.12~P2.14 pins of the LPC2378 are respectively connected to the CLK, SER/PAR, and UPDATE of each ADS112 to provide it with a control clock signal, a serial parallel programming mode selection signal, and a data latch signal. The P2.2~P2.0 and P2.7~P2.3 ​​pins are respectively connected to the A2~A0 and D4~D0 of each AD8112 to provide address and data signals for parallel programming. The P2.8~P2.11 pins are connected to the CE terminals of four AD8112 chips. As needed, four chips can be selected simultaneously for serial programming, or any one chip can be selected for parallel programming, thereby achieving control of the video matrix switching array.

4. Overall design of video matrix

The overall block diagram of the video matrix is ​​shown in Figure 7. The AD8112 array consists of four AD8112 chips. After the 64 signals input by the video input module are switched, 8 signals are output through the video output module, thereby realizing the switching of 64×8 video information. The Ethernet interface module DM9161A peripheral circuit PHY chip is connected to the LPC2378 through the RMII interface, so that the Ethernet communication function is easy to realize. The RS485 communication module controls the camera pan/tilt in the form of serial communication.

5 Video matrix control word sending software design

The software flow of the video matrix control word sending is shown in Figure 8. The video matrix stores the control word transmitted via Ethernet in the control command data buffer area, and selects serial programming mode or parallel programming mode to send according to the requirements of the programming mode.

Conclusion

This paper designs a video matrix switching device based on LPC2378 and ADS112. This device is a video matrix switching device based on embedded system and with network interface. Through μC/OS-II embedded operating system, lightweight TCP/IP protocol stack can be transplanted, which is convenient for network communication, system expansion and transplantation, and better solves the switching problem of video matrix.