Three methods of FPGA frequency measurement (direct measurement method, indirect measurement method, equal precision measurement method)

The actual measured frequency value: clk_fx = X * fs / Y ----Y will have a measurement error of 1 cycle

Measurement error = |(clk_fxe - clk_fx) / clk_fxe | ✖ 100% = 1 / Y ✖ 100%

Therefore, the larger the measured Y is, the smaller the measured error value is. When the gate time is longer, Y is larger; the higher the reference clock frequency is, the larger Y is. Therefore, by increasing the reference clock frequency or increasing the gate time (but it will make the measurement too long, so a trade-off is needed), the measurement accuracy can be effectively improved.

4.3 Verilog Code

The Verilog source code is as follows:

//Equal precision measurement method (low frequency)

module cymometer_equal (   

        input clk_fs ,    

        input rst_n ,            

        input clk_fx , 

        output reg [63:0] fre      

);

parameter CLK_FS = 26'd50_000_000;           

parameter GATE_TIME = 16'd100;    //Gate time, the larger the gate time, the smaller the error, but the measurement time will also be longer    

//reg define

reg                gate_fx ;    //Gating signal, under the measured signal domain         

reg                gate_fs; //Gating signal synchronized to the reference clock

reg                gate_fs_r;          //Register used to synchronize gate signals

reg                gate_fs_d0; //Used to collect the falling edge of the reference clock gate

reg                gate_fs_d1; //Used to collect the falling edge of the base clock gate

reg                gate_fx_d0;          //Used to collect the gate falling edge of the clock under test

reg                gate_fx_d1; //Used to collect the gate falling edge of the clock under test

reg [15:0]    gate_cnt ;          // gate count

reg [31:0]    fs_cnt ; //Count value of the reference clock within the gated time

reg [31:0]    fs_cnt_temp ; //fs_cnt temporary value

reg [31:0]    fx_cnt ; //Count value of the clock under test within the gate time

reg [31:0]    fx_cnt_temp ; //fx_cnt temporary value

//wire define

wire neg_gate_fs;            //Falling edge of the gate signal under the reference clock =

wire neg_gate_fx;            //Falling edge of the gate signal under the clock under test

//Capture the falling edge of the signal

assign neg_gate_fs = gate_fs_d1 & (~gate_fs_d0);

assign neg_gate_fx = gate_fx_d1 & (~gate_fx_d0);

//Detect gate_fx falling edge

always @(posedge clk_fx or negedge rst_n) begin

    if(!rst_n) begin

        gate_fx_d0 <= 1'b0;

        gate_fx_d1 <= 1'b0;

    end

    else begin

        gate_fx_d0 <= gate_fx;

        gate_fx_d1 <= gate_fx_d0;

    end

end

//Detect gate_fs falling edge

always @(posedge clk_fs or negedge rst_n) begin

    if(!rst_n) begin

        gate_fs_d0 <= 1'b0;

        gate_fs_d1 <= 1'b0;

    end

    else begin

        gate_fs_d0 <= gate_fs;

        gate_fs_d1 <= gate_fs_d0;

    end

end

//The clock gate counter under test

always @(posedge clk_fx or negedge rst_n) begin

    if(!rst_n)

        gate_cnt <= 16'd0; 

    else if(gate_cnt == GATE_TIME*2)

        gate_cnt <= 16'd0;

    else 

        gate_cnt <= gate_cnt + 1'b1;

end

//Generate the clock gate under test

always @(posedge clk_fx or negedge rst_n) begin

    if(!rst_n)

        gate_fx <= 1'b0;     

    else if(gate_cnt == GATE_TIME)

        gate_fx <= 1'b1;

    else if(gate_cnt == GATE_TIME*2)

        gate_fx <= 1'b0;

    else 

        gate_fx <= gate_fx;

end

//Synchronize the gate from the clock domain under test to the reference clock domain

always @(posedge clk_fs or negedge rst_n) begin

    if(!rst_n) begin

        gate_fs_r <= 1'b0;

        gate_fs <= 1'b0;

    end

    else begin

        gate_fs_r <= gate_fx;

        gate_fs <= gate_fs_r;

    end

end

//Count the measured signal in the measured clock domain

always @(posedge clk_fx or negedge rst_n) begin

    if(!rst_n) begin

        fx_cnt_temp <= 0;

        fx_cnt <= 0;

    end

    else if(gate_fx)

        fx_cnt_temp <= fx_cnt_temp + 1'b1;

    else if(neg_gate_fx) begin

        fx_cnt_temp <= 0;

        fx_cnt <= fx_cnt_temp;

    end

end

//Count the reference clock in the reference clock domain

always @(posedge clk_fs or negedge rst_n) begin

    if(!rst_n) begin

        fs_cnt_temp <= 0;

        fs_cnt <= 0;

    end

    else if(gate_fs)

        fs_cnt_temp <= fs_cnt_temp + 1'b1;

    else if(neg_gate_fs) begin

        fs_cnt_temp <= 0;

        fs_cnt <= fs_cnt_temp;

    end

end

// Output the result in the reference clock domain

always @(posedge clk_fs or negedge rst_n) begin

    if(!rst_n) begin

        fre <= 0;

    end

    else if(gate_fs == 1'b0)

        fre <= (CLK_FS * fx_cnt ) / fs_cnt;

end

endmodule 

4.4 Simulation Analysis

Testbench:

        The designed measured signal period is 489*2=978ns, so its theoretical frequency is 1/978ns=1022494.88Hz

`timescale 1 ns/ 1 ns

//----------------------------------------------------

module tb_cymometer_equal();

reg clk_fs;

reg clk_fx;

reg rst_n;

wire [63:0] fre;

//----------------------------------------------------                          

cymometer_equal cymometer_equal_inst ( 

.clk_fs (clk_fs ) ,

.clk_fx (clk_fx ) ,

.fre (fre ) ,

.rst_n (rst_n )

);

//----------------------------------------------------

initial begin                                                  

clk_fs = 1'b0;

clk_fx <= 1'b0;

rst_n <= 1'b0;

#116 

rst_n <= 1'b1;

end 

//----------------------------------------------------------                                                   

always #10 clk_fs <= ~clk_fs;                                     

always #489 clk_fx <= ~clk_fx;  

endmodule

The simulation results are shown below:

The measurement result in the above figure is 1022494Hz, and the theoretical frequency is 1/978ns=1022494.88Hz. It can be seen that this result is quite accurate.

Next, change the Testbench to compare the effect of the gate time on the measured signal and the effect of the measured signal's own frequency on the measurement (to avoid too long simulation time, the gate time is set to 10 measured signal cycles. Because the reference clock frequency is high, a shorter gate time will not have any effect)

Module 1: The measured signal frequency is 1022494.88Hz (MHz level)

Module 2: The measured signal frequency is 76103.5Hz (KHz level)

Module 3: The measured signal frequency is 21.217 Hz (Hz level)

The simulation results are as follows:

The measurement results are organized into the following table:

From the test results in the above table, it can be found that the equal-precision measurement method is applicable to both high and low frequency domains, and the measurement result error is only related to the reference clock frequency.

It should be noted here that because the measurement results are all integers (FPGA automatically truncates decimals), if the measured frequency is low, the error will increase because the decimals are truncated. A more convenient solution is to magnify the calculation formula by a certain multiple, so that the "decimal point moves forward". Multiplying the measurement result by 1000 can eliminate the error caused by decimal truncation to a certain extent. The test result of module 3 is 21.217Hz, and the measurement error is 1.9998e-3%, which is basically in the same order of magnitude as the other two signals. (The specific test process is not given here, you can try it yourself).

5. Summary

The direct measurement method is suitable for measuring high-frequency signals; the higher the frequency and the longer the measurement time, the more accurate the measurement result;

The indirect measurement method is suitable for measuring low-frequency signals, but the measurement accuracy depends on its own frequency;

The relative error of the equal-precision measurement method has nothing to do with the frequency of the measured signal, but only with the gate time and the reference clock frequency, which means that equal-precision measurement of the entire test frequency band is achieved. The longer the gate time and the higher the reference clock frequency, the smaller the relative error of the frequency measurement.