Three methods of FPGA frequency measurement (direct measurement method, indirect measurement method, equal precision measurement method)

1. FPGA frequency measurement?

Frequency measurement is often used in the field of electronic design and measurement, so the study of frequency measurement methods is of great significance in practical engineering applications.

There are three common frequency measurement methods: direct measurement method, indirect measurement method, and equal-precision measurement method.

2. Direct measurement method

2.1 Methods

The direct measurement method is also called the frequency measurement method, which is to count the number of pulses of the measured signal within a fixed time t, and then calculate the number of pulses per unit time, which is the frequency of the measured signal.

The signals in the figure below are:

sys_clk: system base clock

gate: A gate signal generated according to a reference clock, used to generate a fixed time (e.g. 1s, for easy calculation)

clk_fx: signal under test

gate is a fixed-time signal generated under the reference clock, and its duration Tg = sys_clk ✖ count number N (settable); during the time that gate is continuously high, the measured signal clk_fx can be used to count it, and the count number is cnt (5 in the figure), then the period of cnt measured signals is the gate duration.

The essence of this method is: using two clocks to measure time in the same period of time, then Tg = Tfx---- Tsys_clk ✖ count number N = Tclk_fx ✖ cnt, after the formula is transformed: clk_fx = cnt ✖ sys_clk / count number N (where clk_fx is the frequency of the signal to be measured, and sys_clk is the reference clock frequency)

2.2 Error Analysis 

As can be seen from the figure, when the gate is at a high level, the measured signal actually has almost six cycles included, but because the measured signal is an asynchronous signal relative to the system and has a different phase, the first cycle cannot be sampled, so the actual sampling is 5, and the error caused is one cycle of the measured signal. It can be foreseen that the measurement error caused by this measurement method is one cycle of the measured signal.

Then the theoretically measured accurate frequency is: clk_fxe = cnt ✖ sys_clk / count number N----theoretically cnt has no error

The actual measured frequency value: clk_fx = cnt±1 ✖ sys_clk / count number N----cnt will have a measurement error of one cycle

Measurement error = |(clk_fxe - clk_fx) / clk_fxe | ✖ 100% = 1 / cnt ✖ 100%

Therefore, the larger the measured cnt is, the smaller the measured error value is. The larger the cnt is, the higher the frequency of the measured signal is. Therefore, it can be inferred that this measurement method is suitable for measuring high-frequency signals. In addition, the longer the selected gate time is, the more signals are measured, and the more accurate the measurement is. However, increasing the gate time will bring the problem of too long a measurement time. It is necessary to make a trade-off based on specific needs.

2.3 Verilog Code

The Verilog source code is as follows:

If the gate time is set to 0.5s and the non-gate time is also 0.5s, the measurement data will be updated every 1 second.

Use a counter to generate gate time, and invert the gate time to get the non-gate time

Count the measured signal during the gate time

Update measurement data during non-gate time

Use parameter to define parameters for easy calling and modification

//Direct measurement method (high frequency)

module cymometer_direct(

input sys_clk , //reference clock, designed to be 50M (changeable)

input sys_rst_n , //reset signal, low level is valid

input clk_fx , //Signal to be tested

output reg [31:0] fre //measurement result

);

parameter TIME_SYS = 20 ; //System clock period: 20ns--frequency = 50MHz

parameter TIME_GATE = 500_000_000 ; //500ms gate setting time, unit: ns

localparam N = TIME_GATE / TIME_SYS; //Generate the number of gates to be counted

reg gate ; //gate

reg [31:0] cnt_gate ; //Counter used to generate gate

reg [31:0] cnt_fx ; //Count the measured signal within the gate time

wire gate_n ; // Gate inversion, used to output the measured frequency value when not in gate state

assign gate_n = ~gate ; // Gate inversion, used to output the measured frequency value when not in gate state

//Frequency division counter, gate time is set to 1ms, then measure once every 2ms

always @(posedge sys_clk or negedge sys_rst_n)begin

if(!sys_rst_n)begin

cnt_gate <= 0;

gate <=0;

end

else begin

if(cnt_gate == N-1)begin

cnt_gate <= 0;

gate <= ~gate;

end

else

cnt_gate<=cnt_gate+1;

end

end 

//Count the measured signal within the gate time

always @(posedge clk_fx or negedge sys_rst_n)begin

if(!sys_rst_n)

cnt_fx <= 0;

else if(gate)

cnt_fx <= cnt_fx + 1;

else

cnt_fx <= 0;

end

//Output the measured frequency value when not in gate

always @(posedge gate_n or negedge sys_rst_n)begin

if(!sys_rst_n)

fre <= 0;

else 

//TIME_GATE/cnt_fx=specified time/number of measured signals=measured signal period, the reciprocal is the frequency

fre <= 1000_000_000/TIME_GATE * cnt_fx;

end

endmodule

2.4 Simulation Analysis

Testbench:

        The designed measured signal period is 489*2=978ns, so its theoretical frequency is 1/978ns=1022494.88Hz; 

`timescale 1ns/1ns //time unit/precision

//----------------------------------------------------

module tb_cymometer_direct();

reg sys_clk;

reg sys_rst_n;

reg clk_fx;

wire [31:0] fre;

// defparam cymometer_direct_inst.TIME_GATE = 500_000; //address width

//----------------------------------------------------

cymometer_direct cymometer_direct_inst(

.sys_clk (sys_clk ),

.sys_rst_n (sys_rst_n ),

.clk_fx (clk_fx ),

.fre        (fre )

);

//----------------------------------------------------

initial begin

sys_clk = 1'b0; //The initial clock is 0

sys_rst_n <= 1'b0; //initial reset

clk_fx <= 1'b0;

#5 //After 5 clock cycles

sys_rst_n <= 1'b1; //Pull high to reset, the system enters working state

// #2500_000

// forever #2560 clk_fx = ~clk_fx;

end

//----------------------------------------------------------

always #10 sys_clk = ~sys_clk; //System clock period 20ns

always #489 clk_fx = ~clk_fx; //Measured signal period 489*2ns = 978ns

endmodule

The simulation is as follows:

In the above figure, the number of measured signals cnt_fx measured within the gate time is 511248, and the measured signal frequency is 1022496Hz; the theoretical frequency = 1/978ns = 1022494.88Hz (MHz level).

It can be seen that this measurement result is relatively accurate, because the gate time is long enough and the frequency of the measured signal itself is relatively high (about 1Mhz).

Next, change the Testbench to compare the effect of the gate time on the measured signal and the effect of the measured signal's own frequency on the measurement:

Module 1: The measured signal frequency is 1022494.88Hz (MHz level), and the gate time is 0.5s

Module 2: The measured signal frequency is 1022494.88Hz (MHz level), and the gate time is 0.5ms

Module 3: The measured signal frequency is 76103.5Hz (KHz level), and the gate time is 0.5s

Module 4: The measured signal frequency is 21.217 Hz (Hz level), and the gate time is 0.5 s

//Multivariate comparison test

`timescale 1ns/1ns //time unit/precision

//----------------------------------------------------

module tb_cymometer_direct();

reg sys_clk;

reg sys_rst_n;

reg clk_fx1;

reg      clk_fx2;

reg        clk_fx3;

reg      clk_fx4;

wire [31:0] fre1;

wire [31:0] fre2;

wire [31:0] fre3;

wire [31:0] fre4;

 defparam cymometer_direct_inst2.TIME_GATE = 500_000; //Reset gate time to 1ms

//----------------------------------------------------

cymometer_direct cymometer_direct_inst1(

.sys_clk (sys_clk ),

.sys_rst_n (sys_rst_n ),

.clk_fx (clk_fx1 ),

.fre        (fre1 )

);

cymometer_direct cymometer_direct_inst2(

.sys_clk (sys_clk ),

.sys_rst_n (sys_rst_n ),

.clk_fx (clk_fx2 ),

.fre        (fre2 )

);

cymometer_direct cymometer_direct_inst3(

.sys_clk (sys_clk ),

.sys_rst_n (sys_rst_n ),

.clk_fx (clk_fx3 ),

.fre        (fre3 )

);

cymometer_direct cymometer_direct_inst4(

.sys_clk (sys_clk ),

.sys_rst_n (sys_rst_n ),

.clk_fx (clk_fx4 ),

.fre        (fre4 )

);

//----------------------------------------------------

//----------------------------------------------------

initial begin

sys_clk = 1'b0; //The initial clock is 0

sys_rst_n <= 1'b0; //initial reset

clk_fx1 <= 1'b0;

clk_fx2 <= 1'b0;

clk_fx3 <= 1'b0;

clk_fx4 <= 1'b0;

#5 //After 5 clock cycles

sys_rst_n <= 1'b1; //Pull high to reset, the system enters working state

end

//----------------------------------------------------------

always #10 sys_clk = ~sys_clk; //System clock period 20ns

always #489 clk_fx1 = ~clk_fx1; //The measured signal period is 489*2ns, and the theoretical frequency is 1022494.88Hz (MHz level)

always #489 clk_fx2 = ~clk_fx2; //The measured signal period is 489*2ns, and the theoretical frequency is 1022494.88Hz (MHz level)

always #6570 clk_fx3 = ~clk_fx3; //The measured signal period is 6570*2ns, and the theoretical frequency is 76103.5Hz (KHz level)

always #23565678 clk_fx4 = ~clk_fx4; //The measured signal period is 23565678*2ns, the theoretical frequency is 21.217Hz (Hz level)

endmodule

The measurement results are as follows: 

The measurement results are organized into the following table:

From the test results in the above table, the following conclusions can be drawn about the direct measurement method:

The longer the gate time, the more accurate the measurement result, but it will also cause a single measurement time to be too long.

The direct measurement method is suitable for measuring high-frequency signals. The measurement error is related to the gate time and the frequency of the measured signal.

3. Indirect measurement method