Three methods of FPGA frequency measurement (direct measurement method, indirect measurement method, equal precision measurement method)

3.1 Methods

The indirect measurement method is also called the period measurement method, that is, within the period of a measured signal, the number of reference clocks is measured to obtain the period of the measured signal, and then convert it into frequency.

The signals in the figure below are:

sys_clk: system base clock

clk_fx: signal under test

During the time when the measured signal clk_fx is at a high level, the reference clock is used for counting, and the number of counts is cnt (8 in the figure), then the cnt✖reference clock period = half the period of the measured signal.

So cnt/FERQ_SYS (reference clock frequency) = (1/2) * (1/clk_fx), after simplification clk_fx = FERQ_SYS/(cnt*2)

 This method is suitable for measuring low-frequency signals, but it also brings the problem of slow measurement speed. The error comes from a system reference clock.

3.2 Error Analysis

As can be seen from the figure, during the high level period of the measured signal, the measured signal is actually included in about 8.5 cycles, but because the measured signal is an asynchronous signal relative to the system and has a different phase, the actual sampling is 8, which causes an error of 1 reference signal cycle. It can be foreseen that the measurement error caused by this measurement method is one reference signal cycle.

Then the theoretically measured accurate frequency: clk_fx = FERQ_SYS/(cnt*2)----theoretically cnt has no error

The actual measured frequency value: clk_fx = FERQ_SYS/((cnt±1)*2)----cnt will have a measurement error of one cycle

Measurement error = |(clk_fxe - clk_fx) / clk_fxe | ✖ 100% = 1 / cnt ✖ 100%

Therefore, the larger the measured cnt is, the smaller the measured error value is. The larger the cnt is, the lower the frequency of the measured signal is (the higher the period is). Therefore, it can be inferred that this measurement method is suitable for measuring low-frequency signals.

2.3 Verilog Code

The Verilog source code is as follows:

Use the reference clock to count during the high level of the signal under test

Update the measurement data during the low level period of the measured signal

Use parameter to define parameters for easy calling and modification

//Indirect measurement method (low frequency)

module cymometer_indirect(

input sys_clk , //reference clock, designed to be 50M (changeable)

input sys_rst_n , //reset signal, low level is valid

                                    //Signal to be tested

input clk_fx , //measurement result

output reg [31:0] fre

);

parameter TIME_SYS = 20 ; //System clock period: 20ns--frequency = 50MHz

reg [31:0] cnt_fx; //Counter for counting the high level of the measured signal

//Counting during the high level of the measured signal

always @(posedge sys_clk or negedge sys_rst_n)begin

if(!sys_rst_n)

cnt_fx <= 0;

else if(clk_fx)

cnt_fx <= cnt_fx+1;

else

cnt_fx <= 0;

end

//Output measurement data during the low level period of the measurement signal

always @(negedge clk_fx or negedge sys_rst_n )begin

if(!sys_rst_n)

fre<=0;

else

fre<=1000_000_000/(TIME_SYS*cnt_fx*2);

end

endmodule

3.4 Simulation Analysis

Testbench still uses the three frequency settings used in direct measurement testing

The measured signal period of module 1 is 23565678*2ns, and the theoretical frequency is 21.217Hz (Hz level)

The measured signal period of module 2 is 6570*2ns, and the theoretical frequency is 76103.5Hz (KHz level)

The measured signal period of module 3 is 489*2ns, and the theoretical frequency is 1022494.88Hz (MHz level)

`timescale 1ns/1ns //time unit/precision

//----------------------------------------------------

module tb_cymometer_indirect();

reg sys_clk;

reg sys_rst_n;

reg clk_fx1;

reg clk_fx2;

reg clk_fx3;

wire [31:0] fre1;

wire [31:0] fre2;

wire [31:0] fre3;

//----------------------------------------------------

cymometer_indirect cymometer_indirect_inst1(

.sys_clk (sys_clk ),

.sys_rst_n (sys_rst_n ),

.clk_fx (clk_fx1 ),

.fre        (fre1 )

);

cymometer_indirect cymometer_indirect_inst2(

.sys_clk (sys_clk ),

.sys_rst_n (sys_rst_n ),

.clk_fx (clk_fx2 ),

.fre        (fre2 )

);

cymometer_indirect cymometer_indirect_inst3(

.sys_clk (sys_clk ),

.sys_rst_n (sys_rst_n ),

.clk_fx (clk_fx3 ),

.fre        (fre3 )

);

//----------------------------------------------------

initial begin

sys_clk = 1'b0; //The initial clock is 0

sys_rst_n <= 1'b0; //initial reset

clk_fx1 <= 1'b0;

clk_fx2 <= 1'b0;

clk_fx3 <= 1'b0;

#5 //After 5 clock cycles

sys_rst_n <= 1'b1; //Pull high to reset, the system enters working state

end

//----------------------------------------------------------

always #10 sys_clk = ~sys_clk; //System clock period 20ns

always #23565678 clk_fx1 = ~clk_fx1; //The measured signal period is 23565678*2ns, the theoretical frequency is 21.217Hz (Hz level)

always #6570 clk_fx2 = ~clk_fx2; //The measured signal period is 6570*2ns, and the theoretical frequency is 76103.5Hz (KHz level)

always #489 clk_fx3 = ~clk_fx3; //The measured signal period is 489*2ns, and the theoretical frequency is 1022494.88Hz (MHz level)

endmodule

The simulation is shown in Figure 1:

The measurement results are organized into the following table:

From the test results in the above table, we can make the following summary about the indirect measurement method: the indirect measurement method is suitable for measuring low-frequency signals, and the measurement error is related to the measured signal frequency.

It should be noted that the output signal cannot process floating point numbers. The recommended solution is to amplify it by an integer multiple (100 times) in order to achieve frequency measurement of the decimal point (otherwise the truncation of the decimal point will cause additional errors).

Multiplying the measurement result by 1000 can eliminate the error caused by decimal truncation to a certain extent. The test result of module 1 is 21.217Hz, and the measurement error is 1.9998e-3%, which is much lower than the other two high-frequency signals. (The specific test process is not given here, you can try it yourself).

4. Equal precision measurement method

4.1 Concept

Both of the above methods will produce an error of ±1 measured clock cycle, which has certain limitations in practical applications. Moreover, based on the measurement principles of the two methods, it is easy to find that the frequency measurement method is suitable for measuring high-frequency clock signals, while the period measurement method is suitable for measuring low-frequency clock signals. However, neither method can meet the measurement requirements of high and low frequencies with the same accuracy.

The equal-precision measurement method is different from the previous two methods. Its biggest feature is that the actual gate time measured is not a fixed value. It is related to the measured clock signal and is an integer multiple of the measured clock signal period. Under the actual gate signal, the clock periods of the standard clock and the measured clock signal are counted at the same time, and then the clock frequency of the measured signal is calculated by the formula. Since the actual gate signal is an integer multiple of the measured clock period, the error of ±1 clock period generated by the measured signal is eliminated, but an error of ±1 clock period of the standard clock signal will be generated. The standard clock usually has an extremely high frequency, so the error is greatly reduced compared with the previous two methods.

The relative error of this measurement method has nothing to do with the frequency of the measured signal, but only with the gate time and the reference clock frequency, which means that the entire test frequency band can be measured with equal precision. The longer the gate time, the higher the reference clock frequency, and the smaller the relative error of the frequency measurement. It should be noted that in principle, the longer the gate time, the higher the accuracy. However, when measuring low-frequency signals (Hz level), it is recommended to set the gate time to more than ten times the measured signal, otherwise the measurement time will be too long.

After understanding the principle of equal-precision measurement, let's explain the calculation method of the measured clock signal: 

First, the actual gate is generated by the measured signal

The clock cycles of the measured clock signal and the standard clock signal under the actual gate are counted respectively.

The number of cycles of the clock signal under the actual gate is X. Assume that the clock period of the signal under test is Tfx, and its clock frequency fx = 1/Tfx. Thus, we can get the equation: X * Tfx = X / fx = Tx (actual gate) ---- there is no error here.

The number of standard clock signal cycles under the actual gate is Y (the error is 1). Assuming the clock period of the measured signal is Tfs, its clock frequency fs = 1/Tfs, the equation can be obtained: Y * Tfs = Y / fs = Tx (actual gate)----the maximum error here is 1 reference clock cycle.

Combining the two equations, we get an equation that only contains the respective clock cycle counts and clock frequencies: X / fx = Y / fs = Tx (actual gate). Transforming the equation, we get the formula for calculating the clock frequency of the measured clock signal: fx = X * fs / Y.

Substitute the known standard clock signal clock frequency fs and the measured quantities X and Y into the calculation formula to obtain the measured clock signal clock frequency fx. 

4.2 Error Analysis 

According to the previous text and the above figure, it is not difficult to find that the error comes from the fact that when using the reference clock to measure the gate time, there will be an error in the reference clock cycle.

Then the theoretically measured accurate frequency is: clk_fxe = X * fs / Y ---- Theoretically Y has no error