Design of Programmable Periodic Signal Tester Based on ISP Chip

1 Introduction
　　The periodic signal tester is a measuring device that directly uses decimal numbers to display the period of the measured signal. It can measure the period of signals such as sine waves, rectangular waves, and triangle waves. The traditional design uses standard logic devices (such as TTL74 series, CMOS4000 series), and then these devices and other components form a digital system from top to bottom. The number of components used is large, the volume is large, the power consumption is high, and the reliability is poor. This article adopts the popular top-down design method. The ispLSI1016 in-system programmable device produced by LatTIce is selected in the design. Taking the development and design of the periodic signal tester circuit system as an example, the specific method of realizing the digital system with in-system programmable logic devices is explained.
2 Working principle and design scheme of periodic signal tester

2.1 Working Principle
　　The basic principle of the periodic signal tester is to count the standard clock pulses within a complete cycle of the measured signal. Considering the accuracy of the test, the period of the measured signal should be much larger than the period of the standard clock pulse. Assuming that the period of the standard clock pulse is 1μs, the count value of the counter within one cycle of the measured signal is the period of the measured signal, in units of 1μs.

2.2 Principle block diagram of the tester
　　The principle block diagram of the periodic signal tester is shown in Figure 1. The tester is mainly composed of a five-digit decimal counter, a gate control circuit, and a decoding display circuit. In Figure 1, S is the signal to be tested, ST is the start signal, and CLK is the standard clock pulse.

3 Top-Down module design
　　This design adopts modular design method, and realizes the design by mixed input of schematic diagram and ABEL-HDL language. Among them, the control circuit module is named GCOL, which is input by schematic diagram; the counter module is named COUNT, which is realized by cascading five modulo 10 counters, and the modulo 10 counter is input by ABEL-HDL language; the decoding display circuit module is named ALLOC, which displays the count value of the counter in the digital tube in a scanning manner, and is input by ABEL-HDL language. Figure 2 is the top schematic diagram of the periodic signal tester.

3.1 Control circuit design
　　The underlying schematic diagram of the control circuit is shown in Figure 3. After the measured signal ST is sent, the first falling edge of the measured signal S causes the G terminal to output a high level, the gate opens, allowing the standard clock pulse to pass, and the counter starts counting. When the next falling edge of the measured signal arrives,

The G terminal outputs a low level, the gate is closed, and the counter stops counting.

3.2 Counter Design
　　In order to facilitate decoding and display, the counter outputs 8421BCD code with a total of five bits (in order to measure all signals in the low-frequency range). The maximum count value is 99999, which is realized by cascading five decimal up-counters, as shown in Figure 4. Assuming that the period of the standard clock pulse is Tcp, the maximum measurement period of the measured signal is Tmax = 99999Tcp.

　　The decimal up-counter is designed using ABEL-HDL language, where CP is the counter count pulse, provided by the standard clock pulse passing through the gate, and RD is the counter clear signal, provided by the system start signal ST. The ABEL source file list of the modulo 10 counter is as follows:


3.3 Display module design
　　The display module is used to output the count value of the five-digit decimal counter to the LED digital tube for display. Therefore, the decoding of BCD/seven-segment code must be completed first. In order to save the I/O resources of the programmable logic device (which is particularly important when designing a complex digital system), the five digital tubes are displayed in the form of scanning, that is, only one digital tube is driven to display at a time, and the five digital tubes are displayed in turn. As long as the scanning speed is fast enough, the eyes will not be able to detect the flicker due to the existence of visual retention.

    The display module is described in ABEL language as follows:

　　

    After compiling and debugging each resource file from the bottom layer to the top layer, the simulation waveform of the control circuit and the counter output is obtained, as shown in Figure 5. In the figure, SBusi (i = 1, 2, 3, 4, 5, 6) is the counter output displayed in bus mode, and G is the gate signal. As can be seen from the figure, when ST is high, the system is cleared. Then, the falling edge of the measured signal S opens the gate, G = 1, and the counter starts counting until the next falling edge of the measured signal S, the counter stops counting and keeps the measurement result. In the figure, SBus5 is the counter ten thousand digit, SBus4 is the counter thousand digit, SBus3 is the counter hundred digit, SBus2 is the counter ten digit, SBus1 is the counter unit digit, and SBus6 is the counter bus output.

4 Conclusion
　　The digital circuit system designed with programmable logic devices has the outstanding advantages of simple circuits and small size. If the gate signal G in this design is replaced with a high-level pulse with a width of 1 second, and the clock pulse CLK input terminal is replaced with the input of the measured signal, the frequency of the measured signal can be obtained. The biggest feature of using CPLD/FPGA devices to design digital systems is that it realizes the softwareization of hardware design, which reduces the difficulty of design and makes modification very convenient, greatly shortening the product development and design cycle.

references

1 Fu Jiacai. EDA Principles and Applications. Beijing: Chemical Industry Press, 2001
2 Xu Zhijun. Large-Scale Programmable Logic Devices and Their Applications. Chengdu: University of Electronic Science and Technology of China Press, 2000　　
3 Yan Shi. Fundamentals of Digital Electronic Technology. Beijing: Higher Education Press, 1998