Design of Fieldbus Multi-channel Real-time Temperature Acquisition System Based on SOPC

Temperature is a physical quantity that characterizes the degree of hotness or coldness of an object. It is one of the most common and basic parameters in industrial production. Temperature monitoring is often required during the production process. Traditional temperature acquisition systems usually use single-chip microcomputers or digital signal processors (DSP) as microcontrollers to control the operation of analog-to-digital converters (ADCs) and other peripheral devices; however, high-speed multi-channel temperature acquisition systems based on single-chip microcomputers or DSPs have certain shortcomings. Since the clock frequency of the single-chip microcomputer is low and the single-chip microcomputer is based on sequential language, various functions must be realized by the operation of software. Therefore, as the amount of programs increases, if the robustness of the program is not good, "program runaway" and "reset" phenomena will occur. DSP has a fast computing speed and has certain advantages in processing complex multiplication and addition operations, but it is difficult to complete the complex hardware logic control of peripheral devices. Therefore, it is difficult for single-chip microcomputers or DSPs to meet the requirements of real-time and synchronization when performing multi-channel temperature acquisition in complex industrial sites. In view of this, this paper introduces a multi-channel real-time temperature acquisition system based on SOPC technology. The system has a short development cycle, flexible resource allocation, and good stability, which meets the application in the field of industrial production with high requirements for real-time and synchronization of temperature acquisition.

1 Overall structure of the system

The hardware of the temperature acquisition system mainly consists of a temperature acquisition module, a data storage module, an FPGA logic control module, and a communication module. Its overall architecture is shown in Figure 1.

After the system is powered on, the static memory EPCS16 automatically loads the configuration data into the SDRAM (HY57V641620) of the FPGA (EP2C8Q208C of the CycloneII series), that is, the digital logic circuit solidified in it is mapped to the FPGA device. The temperature sensor unit AD590 first collects the temperature signal, and then processes it through the signal conditioning circuit to make the output amplitude of the signal meet the range requirements of A/D sampling. At this time, the FPGA controls the analog selection switch ADG706 to select the channel, and controls multiple 16-bit A/D converters ADS8402 to perform A/D conversion, and stores the collected real-time data in two FIFO-type, 16K×9-bit memories IDT72V06 in time-sharing. Then, the data in the IDT72V06 in the read state is read out, and the data is transmitted to the host computer through the PROFIBUS bus through the FPGA control SPC3 communication module.

2 Temperature Acquisition System Design

2.1 Temperature acquisition module

The temperature acquisition module consists of four parts: multiple temperature sensor units, multiple signal conditioning circuits, multiple analog switch circuits and multiple A/D converters.

The temperature sensor unit uses a thermocouple. It has the following advantages: wide temperature measurement range, stable performance; high measurement accuracy, the thermocouple is in direct contact with the object being measured and is not affected by the intermediate medium; fast thermal response time, the thermocouple reacts flexibly to temperature changes; large measurement range, -40 ~ +1600 ℃ can be continuously measured; reliable performance, good mechanical strength; long life, easy installation, especially suitable for real-time temperature detection in complex industrial production processes.

The multi-channel analog switch circuit uses a 16-channel analog selection switch ADG706. The input of its 4-bit address bits. A0, A1, A2, A3 is directly controlled by the FPGA's I/O ports CH0, CH1, CH2, CH3 to determine the channel to be output among the 16 input signals. Each channel selection instruction will simultaneously start the corresponding temperature acquisition channel of multiple ADG706 chips. Then start the corresponding temperature acquisition channel for A/D conversion. This design uses the high-speed successive approximation register (SAR) analog-to-digital converter ADS8402. The start conversion pins of multiple ADS8402 A/D converters share an FPGA I/O port A/D Start. The high and low byte control pins BYTE of the ADS8402 A/D conversion result and the data output control of ADS8402 are controlled by separate I/Os of the FPGA. Every time the FPGA gives a 100ns negative pulse to the A/DStart port, multiple ADS8402 chips can be started to collect data on the corresponding channels. After the conversion is completed, the A/D conversion result can be read by controlling the BYTE port and temporarily stored in the corresponding data unit.

2.2 Data Storage Module

The multi-channel acquisition signal has many paths and a large amount of data to be processed, so an external data storage module is needed to cache the FPGA processing results. At the same time, due to the multi-tasking nature of the host computer, it is impossible for it to read data exclusively from the parallel port. In order to ensure that the FPGA control core communicates with the host computer and reads a large amount of data at one time, this system uses two asynchronous FIFO chips IDT72V06, which have a storage capacity of 16K×9 bits and an access time of 15 ns. One of them is used to store the collected data, and the other is used to read the collected data stored in the FIFO in order to communicate with the host computer through the parallel port. During the operation of the system, the two FIFO bits are expanded to perform double-buffer ping-pong control, and read and write operations are performed in turn, which can greatly improve the parallel port communication speed and data throughput.

2.3 Communication Module

PROFIBUS-DP is an optimized high-speed, low-cost communication connection method, designed for communication between automatic control systems and device-level distributed I/O. It is used for high-speed data transmission in distributed control systems and realizes high-speed data communication between automatic control systems and distributed peripheral I/O devices and intelligent field instruments. SPC3 integrates all PROFIBUS-DP protocols. SPC3 will complete all DP-SAP settings in DP mode.

SPC3 integrates 1.5 KB of dual-port RAM, including parameter registers, mode registers, status registers and interrupt controllers. The watchdog timer integrated in SPC3 has three working states: baud rate detection, baud rate control and slave control. The internal USART can realize the mutual conversion between parallel data stream and serial data stream. The micro sequence controller controls the entire working process, and the idle timer directly controls the serial bus timing. The design of the communication module uses the PROFIBUS-DP dedicated communication protocol chip SPC3, which can accelerate the execution of communication and reduce the burden on the microprocessor.

2.4 FPGA logic control module

The acquisition control unit based on FPGA adopts a top-down modular design method and uses Verilog HDL language to complete the design of each control module. The FPGA logic control module includes A/D sampling control module, FIFO read-write control module and SPC3 control module.

2.4.1 A/D sampling control module

The A/D sampling control module is responsible for controlling the selection of multiple analog inputs of the external ADS8402 chip and realizing reasonable control of the A/D sampling process.

Since ADS8402 uses time-sharing conversion for 16 channels of analog quantity, channel selection must be performed while starting the conversion. ADS8402 sets 4 channel address lines A0, A1, A2, A3, and address latch enable signal ALE. When ALE becomes high, the channel number determined by the A0, A1, A2, A3 codes is latched, and the analog quantity of the channel is connected to the A/D converter for conversion. Based on this characteristic, a hexadecimal counter with a reset terminal is designed, and its counting output terminals Q3, Q2, Q1, and Q0 are connected to the 4 address lines of ADS8402 respectively. The counter is reset on power-on to ensure that the system starts sampling from channel 0. The conversion end signal EOC of ADS8402 is used as the clock signal of the counter to realize the automatic start of sampling control of the next analog input after the conversion of one channel is completed.

The control of the A/D sampling process is implemented using a finite state machine, which divides the sampling process of a certain channel into 7 states, as shown in Figure 2. First, the S0 state initializes each control signal. In the S1 state, the rising edge of the ALE signal is generated to latch the channel address. The start signal START should be generated on the same clock falling edge as the ALE signal. Since the VHDL language does not allow the two edges of the clock to be used as sensitive variables in the same process, the START signal is listed as a state S2 to start the conversion. After starting the conversion, the ADS8402 sets EOC to a low level and sets the S3 state to wait for the A/D conversion to end. After the conversion is completed, the EOC signal is converted from a low level to a high level, and the state machine enters the S4 state and turns on the output enable OE. The state machine enters the S5 state and turns on the data latch signal LOCK to latch the data. In order to generate a signal for communication with other processes, the state machine sets S6 as the last state and then jumps back to the SO initial state. [page]

2.4.2 FIFO read and write control module

Two FIFOs are used to perform read and write operations in turn to realize data caching between FPGA and PC. The schematic diagram of the ping-pong transmission control principle is shown in Figure 3, where the solid arrows and dotted arrows represent different read and write data cycles. The input data stream is distributed to FIFO1 and FIFO2 in a timely manner through the input data stream selection unit. In the first buffer cycle, the input data stream is cached in FIFO1. In the second buffer cycle, the input data stream is cached in FIFO2 through the switching of the input data stream selection unit. At the same time, the data of the first cycle cached in FIFO1 is sent to the data stream operation processing module for operation processing through the selection of the output data stream selection unit. In the third buffer cycle, the input data stream is cached in FIFO1 through the switching of the input data stream selection unit again. At the same time, the data of the second cycle cached in FIFO2 is sent to the data stream operation processing module for operation processing through the switching of the output data stream selection unit. This cycle repeats over and over again.

2.4.3 SPC3 control module

Since SPC3 integrates the complete DP protocol, the FPGA does not need to participate in processing the DP state machine when communicating. The main task is to transfer the data received by SPC3 according to the interrupt generated by SPC3, organize the data to be sent through SPC3, and organize external diagnosis according to requirements. Before SPC3 works normally, it needs to be initialized to configure the required registers, including setting the interrupt enable of the protocol chip, writing the slave identification number and address, setting the SPC3 mode register, setting the diagnostic buffer, configuring the buffer, address buffer, initialization length, and deriving the pointers of each buffer and the pointer of the auxiliary buffer according to the above initial values. The control flow of the communication module is shown in Figure 4.

3 FPGA Implementation of the System

3.1 Nios II System Architecture Design

The Nios II system module includes: Nios II processor, Avalon bus, parallel input/output port PIO, serial peripheral interface SPI, timer Timer, on-chip memory EPCS, off-chip memory SDRAM, and PROFIBUS-DP customized logic. The Nios II processor completes program control and is mainly responsible for temperature collection and data storage operations, and controls the PROFIBUS-DP communication process. Its architecture is shown in Figure 5.

3.2 System Software Design

The software design of the Nios II processor is to store a C/C++ language control program in the soft core. To control the operation of the system, it can read and write the storage unit of the chip and communicate with peripheral devices. In this system, the task of the Nios II program is: within the specified cycle, the FPGA receives the sampling task and control parameters issued by the host computer through the communication module, and then controls the analog selection switch ADG706 and the A/D converter ADS8402 to condition and A/D convert the analog signal of the selected channel, and read the sampling data to transmit it to the off-chip FIFO cache in a ping-pong data transmission mode, and then transmit the sampling data to the host computer through the PROFIBUS-DP communication interface. The main program flow is shown in Figure 6.

Conclusion

The FPGA-based multi-channel real-time temperature acquisition system uses Nios II soft-core processor to implement SOPC, which further simplifies the hardware design. Compared with the traditional MCU-based multi-channel temperature acquisition system, this system has the advantages of flexible resource configuration, stable and reliable operation, and strong real-time performance. In addition, the system has a standard PROFIBUS-DP interface, and as a DP slave station, it can communicate with a variety of DP masters and can be widely used in PROFIBUS distributed control systems in the field of industrial production.