Linux kernelPCIE
Click on the blue " Linux " in the upper left corner and select " Set as Star "
Author: Oda BSP
This article mainly summarizes the basic knowledge of PCIE.
1. PCI bus
In the PC era, in order to solve the problems of CPU frequency and external device access speed, several generations of I/O buses were developed:
1. First generation bus: ISA, EISA, etc.
2. Second generation bus: PCI, PCI-X, etc.
3. Third generation bus: PCIE, mPCIE, m.2, etc.
PCI (Peripheral Component Interconnect), peripheral device interconnection, proposed by Intel, its main function is to connect external devices. The PCI pins are as follows:
PCI pin
The characteristics of PCI bus are as follows:
1. The PCI bus is a parallel bus with 32/64 address lines. Addresses and data are transmitted through these 32/64 address lines and are time-shared and multiplexed.
2. Multiple devices can be mounted on the PCI bus at the same time, and the devices are divided into master devices and slave devices. The main device is generally the main control chip PCI controller and needs to be responsible for arbitration on the PCI bus.
3. PCI devices share the bus and determine which device they are currently communicating with through mechanisms such as chip select pins, address ranges, bus numbers, device numbers, and function numbers.
4. PCI bus communication is roughly divided into: configuration phase and address access phase.
5. Configuration phase: The PCI bus controller scans all devices connected to the PCI bus in sequence, accesses the configuration space of the device, knows the type of device and the resources to be applied for, and then assigns the bus number, device number, function number, and address to the device. space and written into the device's configuration space.
6. Address access phase: In the configuration phase, each PCI device is assigned a PCI address range and written into the device register. In the future, the device will monitor the address line. When it detects that the address transmitted on the address line is its own address range, it will deal with.
7. PCI uses a synchronous timing protocol, and there is a clk clock line in the signal line.
8. PCI has three independent physical address spaces: memory address space, I/O address space and configuration space. The configuration space is a physical space unique to PCI, and PCI devices support plug-and-play.
9. The total length of the configuration space defined by the PCI bus specification is 256 bytes. The first 64 bytes of the configuration space are called configuration headers, which are the same for all devices. The main function of the configuration header is to identify the device and define the access method of the host to the PCI card (I/O access or memory access, as well as interrupt information). The remaining 192 bytes are called the local configuration space (device-related area). Define the characteristics of the local bus on the card, the local space base address and range, etc.
in:
1) Vendor ID: Vendor ID, FFFFh is an illegal vendor ID, based on which it is judged whether the PCI device exists.
2) Device ID: Device ID, the ID of a device produced by a certain manufacturer. The driver finds the corresponding driver based on the Vendor ID and Device ID.
3) Base Address0 ~ 5: BAR register for short, which saves the base address of the PCI bus domain used by PCI devices. After the PCI device is reset, the BAR register stores the address space size and type (I/O or MEM) that the device needs to use. If it is MEM, whether it can be prefetched (whether Prefectchable is 1)
4) IRQ Line: IRQ number, supports management of 24 interrupts.
5) IRQ Pin: Interrupt pin. PCI has 4 interrupt pins. This register indicates which pin the device is connected to.
PCI enumeration process: try all BUS/DEV/FUNC combinations to determine whether the manufacturer ID is FFFFh.
Access configuration space method:
Achieved by accessing the 0xCF8h/0xCFCh port.
1) 0xCF8h: CONFIG_ADDRESS, PCI configuration space address port. CONFIG_ADDRESS register format:
31: Enable bit
23~16: bus number
15~11: Device number
10~8: Function number
7~2: Configuration space register number
1~0:0
2) 0xCFCh: CONFIG_DATA, PCI configuration space data port.
2. Introduction to PCIE
PCIE (PCI Express) was developed on the basis of PCI and is currently the most commonly used high-speed bus in PCs and embedded systems. PCIE and PCI are software backward compatible, and PCI system software can be used in PCIe systems.
PCIE uses a tree topology, and the system architecture includes root complex, switch, bridge, endpoint and other types of PCIE devices. The PCIE bus topology is as follows:
Root Complex: Root complex, referred to as RC, is the interface between CPU and PCIE. The RC is at the root of the PCIE inverted topology and communicates with the rest of the system on behalf of the CPU. PCIE ports are marked as root ports in configuration space.
Bridge: Bridge provides an interface with other buses (such as PCI or PCI-X), allowing old PCI or PCI-X cards to be plugged into new systems. Reverse bridging allows a new PCIE card to be plugged into an older PCI system.
Switch: Provides expansion or aggregation capabilities, allowing more devices to be connected to a PCIE port. Acts as a packet router, identifying which path a given packet needs to take based on an address or other routing information. It is a PCIE to PCIE bridge.
Endpoint: The end of the PCIE bus system topology, generally serving as the initiator or terminator of bus operations. Endpoint can only accept data packets from or send data packets to the upper-level topology.
PCIe slots are concentrated in four types: PCIex1/x4/x8/x16.
1) The length of the PCIex1 slot is the shortest, with 14 data pins. Main uses: independent network card, independent sound card and USB3.0/3.1 expansion card.
2) PCIex4 slots are the same as x8 slots. Most of them are now made into PCIex16 slots or expanded to M.2 interfaces for installing M.2 SSD and M.2 wireless network cards.
3) PCIex8. For compatibility, PCIex8 slots are usually made into PCIex16 slots, but only half of the data pins are valid.
4) The PCIex16 slot is mainly used for graphics cards and RAID array cards, and is backward compatible with x1/x4/x8 level devices.
In the PCI bus, all devices that need to submit interrupt requests must be able to submit interrupt requests through the INTx pin. The MSI mechanism is an optional mechanism. In the PCIE bus, the PCIE device must support the MSI or MSI-X interrupt request mechanism, but does not need to support the INTx interrupt message.
In the PCIE bus, the MSI and MSI-X interrupt mechanisms use the memory write request TLP to submit an interrupt request to the processor.
3. PCIE address space
PCIE has three main address spaces: memory-space, IO space and configuration space.
1) Memory space: data storage memory space (refetchable and Non-Prefetchable Memory Space)
2) IO Space: used to access the internal register/storage of IO devices, which has been replaced by the MMIO mechanism. The access method is the same as Memory, and is also divided into (refetchable and Non-Prefetchable Memory range)
3) Configuration Space: Configuration space, controlling Memory space mapping through bar register
4. Differences between PCI and PCIE
1) Color
PCI interfaces are usually white, and PCIE interfaces are generally in other colors.
2) length
The PCIE interface is longer than the PCI interface.
3) Compatibility
PCIE is compatible with current PCI technology and equipment at the software level.
4) speed
PCI operating frequency: 33MHZ and 66MHZ, maximum throughput rate 264MB/s (66MHZ*32BIT/8).
PCI-X operating frequency: 66MHZ/100MHZ and 133MHZ, maximum throughput rate 1064MB/s (133MHZ*64BIT/8).
5) Transmission method
PCI is parallel data transmission, transmitting 4/8 bytes at a time, half-duplex.
PCIE is serial data transmission, full duplex.
6) Hardware
PCI signals are normal levels.
PCIE signals are differential levels.
7) Link
PCI is a bus connection method.
PCIE is a point-to-point connection.
8) Coding method
PCIE gen1 and gen2 use 8bit/10bit encoding, and gen3 and later use 128b/130b encoding.
9) Inbound and outbound
When PCIE devices and system memory access each other, outbound refers to the direction from CPU to device; inbound refers to the direction from device to RC (CPU side). When the CPU reads and writes the registers on the RC side, it belongs to the scope of the upper system and does not belong to inbound or outbound.
10) PCI configuration space
PCI devices have 256B of configuration space, and PCIE also provides an additional 4KB extension. The first 64B of the 256B configuration space are standardized, and the rest are defined by each manufacturer.
PCI device address:
10.1) Bus number: Manufacturer ID
10.2) Device number: Device ID
10.3) Function number: Equipment type
11) PCIE configuration space
PCIE supports a total of 256 buses, 32 dev and 8 fun, which is the same as PCI.
The development of PCIE devices is forward compatible with PCI. The first 256B of each device's configuration space is PCI space, and the space after (4K-256)B is PCIE control space.
Linux uses the same set of driver codes to handle PCI and PCIE drivers, and only needs to distinguish the two bus protocols in low-level operations such as configuration and transmission.
5. PCIE driver
Take the RK3568 PCIE RC driver as an example.
1) compatible = "rockchip,rk3568-pcie", "snps,dw-pcie"
The PCIE interface uses RC mode; EP mode
2) bus-range = <0x10 0x1f>
The PCI bus address range is from 0x10 to 0x1f.
3)interrupts
Interrupt number and interrupt name. The corresponding interrupt number for RK3568 is as follows (-32):
4) interrupt-map-mask and interrupt-map
interrupt-map-mask and interrupt-map: standard PCI attribute values, corresponding to INTA ~ INTD (legacy interrupt)
5) num-lanes = <1>
The number of lanes used by PCIE devices does not need to be adjusted by default. The software automatically detects and closes unnecessary lanes to save power consumption.
6) max-link-speed = <3>
PCIE bandwidth version, 1 represents Gen1; 2 represents Gen2; 3 represents Gen3, no configuration is required.
7) reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>
The perst# reset signal of the PCIE interface is required for both the slot and the soldering equipment. Must be configured.
8) msi-map = <0x1000 &its 0x1000 0x1000>
PCIE devices are mapped to MSI controllers. The format and introduction are as follows:
9) phys = <&pcie30phy>
PCIE PHY used.
10) power-domains = <&power RK3568_PD_PIPE>
PCIE power domain
11) reg and reg-names
PCIE-dbi (configuration space address of the device on the mapped bus) and PCIE-apb (PCIE controller address) register addresses and ranges
12)rangs
Function: The device maps the CPU domain address to the PCIE domain address
Format:
<Mapping type (field 1) PCIe base address (field 2~3) CPU domain base address (field 4~5) Mapping area size (field 6~7)>
0x81000000: indicates IO space
0x82000000: Indicates MEM space (non-prefetchable)
13) vpcie3v3-supply = <&pcie30_3v3>
3V3 power supply for PCIE peripherals. PCIE phy uses 1.8V or 0.9V power supply.
The command to view PCI devices in Linux system is: lspci, PCI logical address: XX:YY:Z respectively represent bus number: device number: function number. A PCI domain can accommodate 256 buses, each bus can support 32 PCI devices, and each PCI device can accommodate 8 PCI functions.
lspci -t: display tree structure
lspci -x: Display the first 64 bytes of the configuration space
lspci -s: Specify PCI device
end
A mouthful of Linux
Follow and reply [ 1024 ] Massive Linux information will be given away
Collection of wonderful articles
Article recommendation
京公网安备 11010802033920号