October 2001
Advanced Information
®
AS7C25512PFS32A
AS7C25512PFS36A
2.5V 512K
×
32/36 pipeline burst synchronous SRAM
Features
• Organization: 524,288 words x 32/36 bits
• Fast clock speeds to 200MHz in LVTTL/LVCMOS
• Fast clock to data access: 3.0/3.5/4.0 ns
• Fast OE access time: 3.0/3.5/4.0 ns
• Fully synchronous register-to-register operation
• Single register “Flow-through” mode
• Single-cycle deselect
- Dual-cycle deselect also available ( AS7C25512PFD32A/
AS7C25512PFD36A)
• Pentium®
*
compatible architecture and timing
• Asynchronous output enable control
• 100-pin TQFP package
• 119-Ball BGA (7 x 17 Ball Grid Array Package)
• Byte write enables
• Multiple chip enables for easy expansion
• 2.5V core power supply
• 2.5V I/O operation
• NTD™
*
pipeline architecture available
(AS7C25512NTD32A/ AS7C25512NTD36A)
* Pentium
®
is a registered trademark of Intel Corporation. NTD™ is a
trademark of Alliance Semiconductor Corporation. All trademarks
mentioned in this document are the property of their respective owners.
Logic Block Diagram:
LBO
CLK
ADV
ADSC
ADSP
A[18:0]
19
CLK
CE
CLR
D
CE
Address
register
CLK
D
Q0
Burst logic
Q1
18
Q
Pin Arrangements:
16
18
512K × 32/36
Memory
array
DQP
c
/NC
DQ
c
DQ
c
V
DDQ
V
SSQ
DQ
c
DQ
c
DQ
c
DQ
c
V
SSQ
V
DDQ
DQ
c
DQ
c
FT
V
DD
NC
V
SS
DQ
d
DQ
d
V
DDQ
V
SSQ
DQ
d
DQ
d
DQ
d
DQ
d
V
SSQ
V
DDQ
DQ
d
DQ
d
DQP
d
/NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
A6
A7
CE0
CE1
BW
d
BW
c
BW
b
BW
a
CE2
V
DD
V
SS
CLK
GWE
BWE
OE
ADSC
ADSP
ADV
A8
A9
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
GWE
BWE
BW
d
DQ
d
Q
Byte write
registers
CLK
DQ
c
Q
Byte write
registers
CLK
D
DQ
b
Q
Byte write
registers
CLK
DQ
a
Q
Byte write
registers
CLK
D
Enable
CE
register
CLK
Power
down
D
Enable
Q
delay
register
CLK
Q
D
D
36/32
36/32
BW
c
BW
b
TQFP 14 × 20 mm
512K x 32A/36A
BW
a
CE0
CE1
CE2
4
OE
Output
registers
CLK
Input
registers
CLK
OE
FT
DATA [35:0]
DATA [31:0]
Note: Pins 1,30,51,80 are NC for ×32
Selection guide
Minimum cycle time
Maximum clock frequency
Maximum pipelined clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
10/3/01; v.0.9.1
-200
5
200
3.0
280
100
30
-166
6
166
3.5
230
70
30
LBO
A5
A4
A3
A2
A1
A0
NC
NC
V
SS
V
DD
A18
A17
A10
A11
A12
A13
A14
A15
A16
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
ZZ
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQP
b
/NC
DQ
b
DQ
b
V
DDQ
V
SSQ
DQ
b
DQ
b
DQ
b
DQ
b
V
SSQ
V
DDQ
DQ
b
DQ
b
V
SS
NC
VDD
ZZ
DQ
a
DQ
a
V
DDQ
V
SSQ
DQ
a
DQ
a
DQ
a
DQ
a
V
SSQ
V
DDQ
DQ
a
DQ
a
DQP
a
/NC
-100
10
100
4.0
150
50
30
1 of 2
Units
ns
MHz
ns
mA
mA
mA
Alliance Semiconductor
Copyright © Alliance Semiconductor. All rights reserved.
AS7C25512PFS32A
AS7C25512PFS36A
®
Pin Configuration
119 BGA Top View
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC
FT
DQC
DQC
V
DDQ
DQC
DQC
V
DDQ
DQd
DQd
V
DDQ
DQd
DQd
NC
NC
V
DDQ
2
A
A
A
DQPc
DQc
DQc
DQc
DQc
V
DD
DQd
DQd
DQd
DQd
DQpd
A
NC
TMS
3
A
A
A
V
SS
V
SS
V
SS
BWc
4
ADSP
ADSC
V
DD
NC
CE0
OE
ADV
GWE
5
A
A
A
V
SS
V
SS
V
SS
BWb
V
SS
NC
V
SS
BWd
V
DD
CLK
NC
BWE
V
SS
NC
VSS
BWa
V
SS
V
SS
V
SS
LBO
A
TDI
A1
A0
V
DD
A
TCK
V
SS
V
SS
V
SS
V
DD
A
TDO
6
A
A
A
DQpb
DQb
DQb
DQb
DQb
VDD
DQa
DQa
DQa
DQa
DQPa
A
NC
NC
7
V
DDQ
NC
NC
DQb
DQb
V
DDQ
DQb
DQb
V
DDQ
DQa
DQa
V
DDQ
DQa
DQa
NC
ZZ
V
DDQ
Note: For P/N AS7C25512PFS32A, 4 of the I/O Pins must be left open (N.C.)
10/3/01; v.0.9.1
Alliance Semiconductor
2 of 2
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responsibility for any errors that may appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change
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