Low Side Gate Driver PCB Layout Tips with Overcurrent Protection
About the Author
Author: Wchu1
Translation: Chen Ziying
Infineon's 1ED44173/5/6 is a new low-side gate driver IC that integrates over-current protection (OCP), fault status output and enable function. This highly integrated driver is very friendly for PFC (digitally controlled power factor correction) applications using boost topology and ground reference.
In PFC applications, shunts are used to sample power switch current or DC bus current. The location of the diverter varies depending on the control method chosen. For example, in Figure 1 Example 1, a shunt is placed between the IGBT emitter and system ground to sample the power switch current when the controller implements peak current control or current balance control in an interleaved PFC application.
In comparison, Figure 1 Example 2 shows a shunt placed between system ground and the negative DC bus in order to sense the DC bus current. This configuration is commonly used for average current mode control, where the digital controller can calculate the input power based on average current and DC bus voltage feedback.
Figure 1: Two different types of low-side gate drivers with OCP: 1ED44176N01F (Example 1) has positive current sensing to meet the requirements of the first shunt position, while 1ED44173/5N01B (Example 2) has negative current sensing to Meets requirements for second diverter location
Application in household air conditioners
In today’s residential air conditioning (RAC) applications with digitally controlled PFC, the controller uses the power feedback signal to implement adaptive DC bus voltage control. This allows lower DC bus voltage to be used to reduce losses at light loads, while switching to the full DC bus when full load is required.
Due to the different shunt configurations, Infineon has designed two different types of low-side gate drivers with OCP: the 1ED44176N01F (Figure 1, Example 1), and the 1ED44173N01B and 1ED44175N01B (Figure 1, Example 2). The former has positive current sensing and satisfies Example 1 shunt configuration, while the latter two have negative current sensing and satisfies Example 2 shunt configuration. The 1ED44175N01B is targeted at driving IGBTs, while the 1ED44173N01B is designed to drive MOSFETs.
Figure 2: Differences in 1ED44173/5/6 functions
In high-current, high-speed switching circuits such as PFC, PCB layout is always a challenge. A good PCB layout can ensure device operating conditions and design stability. Improper components or layout may cause switching instability, excessive voltage ringing, or circuit latch-up.
Best PCB Layout Tips for Gate Driver ICs
1 |
When using an RC filter circuit between the microcontroller and the gate driver, the wiring at the input should be as short as possible (less than 2-3 cm). |
2 |
The EN/FLT output is an open-drain output, so a pull-up resistor is required to pull it to the 5V or 3.3V logic supply. When designing, place the RC filter close to the gate driver. |
3 |
To prevent false triggering in overcurrent protection, the RC filter wiring between OCP and ground should be as short as possible. |
4 |
Mount each capacitor as close to the gate driver pin as possible. |
5 |
Connect the ground of the microcontroller directly to the COM pin (1ED44173/5N01B). |
6 |
Connect the gate output return to COM and connect the ground pin of the microcontroller to the VSS logic ground pin (1ED44176N01F), this prevents noise coupling from the logic input pin to the driver output return. |
Let’s take a look at what the right layout can do. The example below shows the circuit (Fig. 3) and layout implementation (Fig. 4) of a 1ED44175N01B and a TO-247 IGBT (e.g. IKW40N65WR5). With this design, the loop area and inductance of the PCB can be reduced.
Figure 3: Circuit diagram of 1ED44175N01B
Figure 4: PCB layout of the above circuit
How to reduce the area surrounded by PCB traces
to reduce parasitic inductance
Place the 1ED44175N01B close to the gate and emitter of the IGBT
Place the decoupling capacitor (C3) directly on the VCC and COM pins
Place the filter capacitors (C1 and C4) and the fault clear time programming capacitor (C2) close to the pins
Place the ground plane just above or below the 1ED44175N01B to reduce trace inductance
Additionally, the ground plane connected to COM helps act as a radiated noise shield and provides a thermal path for the device to dissipate power. Following these layout tips can eliminate common noise coupling issues and save you development time.
To learn more about 1ED44173/5/6 products, their evaluation boards and in-circuit simulation , please scan the QR code of the respective products below to access.
1ED44173N01B
1ED44175N01B
1ED44176N01F
Figure 5: Online simulation page
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