The renaissance of semiconductors

Major shifts in semiconductors and end markets are driving a technological renaissance, but navigating new multifaceted demands will bring structural changes to the chip industry, and we will find it more difficult for one company to do everything.

Over the past decade, the mobile industry has been the dominant driver of the semiconductor ecosystem, from EDA and IP to foundries. The industry’s growth has reached a plateau, but new drivers are emerging in vertical industries such as automotive, medical and industrial, and in horizontal areas such as artificial intelligence, beyond Moore’s Law, power consumption and thermal constraints.

The disruption appears to be good for the entire semiconductor ecosystem, and innovation is at its highest level in recent memory. “If the ESDMSS’s second quarter report is an indicator, EDA is still growing despite the stagnation in the smartphone industry,” said Bob Smith, executive director of the ESD Alliance. “Chip companies are still designing new end-user products. The report shows that CAE and IC physical design are up significantly, while PCB is down slightly. In the long run, CAE and IC physical design are generally on the rise, which means new chip design activity is going on.”

The industry now has multiple drivers. "Until 10 years ago, you would see there was a big inflection point," said Michal Siwinski, vice president at Cadence. "First it was datacom, then mobile, but that has evolved. In the last five years, it's started to diversify. A lot of innovation was driven by mobile before, but today the tech giants are driving other verticals that rely on large data centers or adding intelligence to all computing, whether it's in consumer products, whether it's in industrial, whether it's in automotive, whether it's in aerospace. That's a good thing, but there are so many drivers."

The divergence between mobile computing and high-performance computing (HPC) is one example. “The end of Dennard’s scaling law (Dennad’s 1974 paper predicting that power consumption would decrease as transistor size decreased) has impacted both parties, but they have responded differently,” said Thom Gregorich, director of business development for SMT at Carl Zeiss. “HPC continues to pursue more advanced fab nodes, enabling multi-core designs and supporting processors with traditional DRAM package arrays. Mobile has caught up with HPC in the pursuit of advanced fab nodes, showing greater purchasing power and dominating the leading-edge fab business. They have also implemented multi-core designs with complex POP-DRAM solutions to address the physical limitations of mobile devices. The end of Moore’s Law hit HPC first and, in part, led to the development of HBM-DRAM and 2.5D packaging to circumvent the DRAM performance wall. Meanwhile, the POP technology portfolio continues to provide sufficient bandwidth for mobile devices.”

Mobile devices are certainly not standing still. “Mobile devices are becoming more and more advanced,” said Vic Kulkarni, vice president and chief strategist at Ansys. “This technology is now being embedded in everything we do, from 5G handsets to base stations, and it will eventually find its way into many other markets. This will generate a lot of mobile data, requiring a lot of compute.”

New Horizons

Horizontal markets cut across all end markets and require the attention of the entire ecosystem. In the past, the typical representative of horizontal was the von Neumann computing architecture, using monolithic CMOS technology and verification. Later, power devices were added. In the past few years, new horizons have become increasingly important, including artificial intelligence, security, and Beyond Moore's Law.

"What's really driving the next step is data," said Michael Sanie, vice president of marketing and strategy at Synopsys. "The impact of data is two-fold. The first is the device that moves the data - the network, which can be any kind of data network chip, broadband or 5G across all end markets. But latency is a challenge, and bandwidth and capacity are limited. Second, we need more data processing - compute. There are two main parts of this, high-performance computing and artificial intelligence chips. Networking and compute are the next drivers."

New computing architectures are emerging. “AI, machine learning, deep learning are everywhere,” said Cadence’s Siwinski. “We talk about pervasive intelligence, and that’s not just a fun word game, it’s because we see aspects of machine learning and deep learning being applied in every vertical market. There’s so much data and compute exploding in every vertical and every single electronic device that supports it that you almost have to add machine learning to be able to use computers more intelligently and more efficiently, or you’re overwhelmed because there’s so much data.”

AI is everywhere. “The increasing adoption of AI across a wide range of markets is one of the most exciting technology advances in a generation,” said Chet Babla, vice president of Arm’s automotive and IoT business. “We are now seeing smart asthma ventilators that use AI to provide better respiratory care, and smart contact lenses that use microelectronics and tiny displays to share critical information with the wearer.”

Even within AI, there are multiple sides to the problem. “From an SoC architecture perspective, think of a 2-by-2 matrix with data center on one side and edge on the other,” said Kurt Shuler, vice president of marketing at Arteris IP. “People will debate where the dividing line is, but you can think of it as one running on battery power and the other having to be plugged in. There are two sides to AI here: one is training a neural network, and the other is using that neural network in the real world to do inference. So you have that 2 x 2 matrix of data center versus edge, training versus inference.”

safety

Another new horizontal is security. “Cybersecurity and anti-piracy are quickly becoming huge challenges,” said Smith of the ESD Alliance. “These affect hardware designers, software and software IP developers, and the entire semiconductor manufacturing ecosystem. ”

Security concerns are pervasive. “We’ve reached a point where almost all chip companies — not necessarily just aerospace and defense, but now automotive — are adopting a ‘trust no one, trust no one’ thought process,” said Synopsys’ Sanie. “We need to provide the methodologies, IP, design technologies, 3D ICs that meet the PPA needs not only today but also in the next five or 15 years, depending on the industry. That means silicon lifecycle management is a huge challenge for customers. It impacts not only design and manufacturing, but it extends to the application. Who can accurately predict the performance challenges and what the security vulnerabilities are going to be throughout the SoC lifecycle?”

Without safety, technological progress may be limited. “Arm is trying to accelerate autonomous decision-making through safety in automotive and industrial applications,” said Arm’s Babla. “Autonomy has the potential to improve every aspect of our lives, but only if it is built on a secure and reliable computing foundation.”

More Than Moore's Law

Moore’s Law was once a universal driver that cut across most vertical markets, especially those that could take advantage of additional area, lower power and benefits from the most advanced nodes. “That driver continues,” Siwinski said. “Everyone said we couldn’t get past certain nodes, but now we’re thriving at 7nm, 5nm, 3nm and exploring at 2nm. About 10 years ago, power became the No. 1 barrier. Now it’s power and thermal intertwined throughout the system, and it’s a lateral factor. ”

Moore’s Law is no longer the only way to go. “The industry is leapfrogging Moore, also known as Beyond Moore,” said Ansys’ Kulkarni. “We have entered the data-centric era, which is driving new vertical markets (see Figure 1). Everything is connected in a bigger and bigger way. That’s why it’s the semiconductor renaissance, because we see the growth of semiconductors, the growth of electronics, and the growth of all the things that feed those things, like photonics, mechanical, thermal for thermal management. All of these impacts follow you into the new world, the data-centric world of Moore’s Law.”

▲ Major trends in the semiconductor industry (Source: Ansys)

Changes like these affect many areas. “People are rethinking design architectures, and that’s really the main differentiator among chipmakers, especially in the HPC and AI chip markets,” Sanie said. “They’re looking for really cool ways to design their chips to take advantage of existing silicon geometries and get really good clock speeds. But they’re also solving problems with better methodologies, better techniques, to get the PPA, performance, and power optimizations they need. And what’s coming is a lot of use of multi-die 3D-IC structures, and ultimately heterogeneous integration of chips.”

“People are extending the divide-and-conquer approach by breaking the system into multiple dies,” Kulkarni said. “You can have different functions on the same class of subsystems, you can have stacked dies, converters, 2.5D structures. A recent example is a smart vision sensor, which is a 3D-IC stack with a CMOS sensor array on an AI chip with a lot of machine learning and artificial intelligence built into the chip to enable not only autonomy but also intelligent decision making for mobile devices.”

Die placement will be constrained by scalable, cost-effective solutions. “Die is one of several packaging technologies evolving in the post-Moore era, including micro-TSVs, micro-solder connections, copper fusion interconnects, high-density organic substrates, and high-density fan-out packaging,” said Carl Zeiss’ Gregorich. “Several prominent semiconductor companies predict that the bump-to-interconnect pitch ratio will exceed 100:1 within the next 10 years. This paradigm shift will have an impact on both HPC and mobile, and we expect each market segment to optimize for its specific needs. For example, die and TSV will be leveraged by both segments. High-density substrate packaging and high-density fan-out packaging will be optimized for each segment. In both areas, successful package solutions will have the following characteristics: (1) they will have an acceptable cost/benefit ratio and be scalable, and (2) they will not adversely affect manufacturing yields or field reliability.”

The advent of die requires changes throughout the design flow. “Several aspects of chip design, such as the control of individual functional modules and, most importantly, the design of interfaces between wafers, between chips or between packages, require specific design,” said Paul Lindner, technical director of the Electric Vehicle Group. “IDMs and foundries that own the building blocks, including interfaces for 3D integration, are taking full advantage of these new integration trends and preparing for them accordingly. At the same time, heterogeneous integration brings business opportunities in packaging, and OSATs are well positioned in this regard.”

Emerging vertical markets

Technologies initially developed in one vertical are now being used to scale other verticals. “The workload that has evolved from smartphones is driving a change in computing technology, and that is autonomous decision making, ” said Babla. “We experience autonomous systems every day, such as when our smartphones unlock automatically using our Facebook, and automated features are becoming more common in vehicles and factory environments. Developers designing autonomous systems need technologies that meet relevant safety standards, are scalable to address workloads and processing power, and are energy efficient and safe. ”

What everyone agrees on is that “one clear market driver is autonomous driving,” Smith said. “This is largely due to the rapid pace of innovation in the automotive market and the recent push for full electrification in many regions.”

That may influence the direction of IP developers. “If you look at the PowerPoint slides 10 years ago, there were 20 application processor vendors and digital baseband modem vendors,” said Arteris’ Shuler. “We focused our business on this market and thought if we satisfied the need, we could satisfy everybody’s need. When you look at our PowerPoint slides today, there are five because they will merge over time. Think about the requirements for automotive today, and we believe that if we satisfy their AI requirements, we can satisfy anybody’s requirements, or nearly anybody’s requirements in the market. So if we satisfy the automotive needs, the needs of people working in robotics or industrial will be satisfied.”

The vertical that people often talk about is the Internet of Things. "The Internet of Things is very interesting because it's a byproduct of recent advances," said Sawhney. "Data is no longer centralized, it's been pushed to the edge. This creates a weird continuum where data is centralized, but it's also being pushed to the edge. At the same time, compute is being centralized, but compute itself is being pushed to the edge. It creates a computing continuum between the cloud, the server, and the edge device, and all of a sudden 5G becomes this big ether between these continua."

Even COVID is impacting vertical markets. “COVID has changed the focus of the market, and new formulations are being developed,” Siwinski said. “This disruption, and disruption in general, either creates opportunity or creates disruption. A lot of the time, technology has created opportunity, and COVID is no different.”

COVID has created the need for more distributed systems. “This direction was already underway, but COVID has definitely accelerated it,” Sanie said. “If you look at the networking and computer companies, their challenges and their requests to us have not stopped because of COVID. In fact, we could say they have accelerated.”

More collaboration

One of the new horizontal and vertical impacts is that everyone in the ecosystem becomes thinner and problems become more widespread, requiring higher levels of collaboration between companies.

“IP vendors and EDA tools have always had very close ties with foundries,” Siwinski said. “Around 10nm, or a little before, the nature of that collaboration started to change. Before, it was mostly innovation on the foundry side, and then the EDA tools and IP adjusted to the new reality. With the new nodes, the collaboration has evolved into a tighter partnership. R&D organizations are working more closely with foundries, not only in support but also in mutual innovation. It fosters faster innovation.”

There are more system issues. “We’re looking beyond electronics, beyond semiconductors, beyond systems,” Kulkarni said. “That includes mechanical, computational fluid dynamics, and photonics. EDA, IP, the entire ecosystem, and the packaging companies, who were considered an afterthought, now have to come together because decisions made in one area also impact other areas, and there needs to be more collaboration. For example, what do you do when power affects timing? There are also thermal distribution issues, so we need to do mechanical stress, warpage, and thermal analysis.”

And within design teams, groups that used to work separately now have to come together. “It’s not like before, where you build a chip and then say, ‘With this chip, what can I do in software?’” Shuler said. “Instead of thinking about what my software has to do, it becomes what do I need to do at the system level? Here’s the new processing element I need to create, here’s the new data flow I need to create to guarantee that I can perform the collection function for the thousands of processing elements that need data at the same time. Whether it’s automotive or AI, even if we’re dealing with horizontal capabilities, we have to be able to understand higher up in the value chain what they’re trying to do.”

It will also require collaboration between EDA tools. “Methodology will become a bigger part, not just to get better power or performance, but an approach that goes beyond SoC optimization and looks at system-level optimization,” Sanie said. “At this point, we have to look at different vertical markets. How do you do power management for automotive chips, high-performance computing chips, and mobile chips? They’re all different. How do you do power management, performance management, and even silicon lifecycle management? Each approach is different. So we have system-level approaches that are more vertical-specific.”

Siwinski agrees. “In fact, we’re asking for new ways of innovating brands to attract new customers. Then other companies use those methods and they become the new standard and the new best practice. It used to be about specific point technologies because the methods came one step at a time. Now, at the engine level, complexity is driving closer local automation between the various technologies.”

The industry is also witnessing higher levels of collaboration between EDA companies or between business units within larger organizations.

in conclusion

New horizons and new verticals are driving innovation across the ecosystem in a way that never happened before. This will create challenges and opportunities and require many companies to decide where they will become experts and where they will collaborate. We have already seen examples of this, but we should expect to see more in the future.

“We’re just beginning to scratch the surface of what’s going to start,” Siwinski said. “I’m not saying this is going to be like a Renaissance, where biological challenges created disruptions that created centuries of different innovations. Granted, it was a very different world two centuries ago, but ultimately you’re looking at one technology opening up opportunities for many different opportunities. Think about firefighters around the world whose jobs are becoming more difficult, and why not take this technology and create a whole new submarket for autonomous firefighting drones.” (This article is compiled from: SEMICONDUCTOR ENGINEERING –BY: BRIAN BAILEY)

Source: Smart Products Product Circle