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TSMC 5nm Acceleration

Latest update time:2019-10-16
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The third quarter corporate briefing of TSMC, the leading foundry company, will be held on the 17th, hosted by President Wei Zhejia and new CFO Huang Renzhao. TSMC's capital expenditure this year remains at a high standard of US$11 billion. The market expects that it will focus on the 5nm large investment plan, including the first phase of Fab 18 to enter mass production after March next year, and the second and third phases of capacity construction will be completed and put into mass production in the next two years. In 2022, the annual production capacity of 5nm wafers will exceed 1 million pieces when the full capacity is put into production.


Equipment manufacturers estimate that TSMC's capital expenditure in 2020 will reach US$12 billion to US$13 billion. The most important investment project is the construction of 5-nanometer extreme ultraviolet (EUV) production capacity, and capital expenditure in 2021 will continue to increase due to the launch of the 3-nanometer project at Fab 18.


Analysts are optimistic that TSMC's major alliance partners, including plant engineering manufacturer Han Tang, recycled wafer manufacturers Sun Semiconductor and China Semiconductor, EUV mask box manufacturer Denso, wafer test card manufacturer Precision Measurement, silicon wafer manufacturer GlobalWafers, and testing service manufacturers iST and Hong Kang, will directly benefit.


TSMC's 5nm process is a culmination of technologies. Its enhanced 7nm process (N7+) has been mass-produced using EUV lithography technology. As it has gone through the new technology learning curve, the 5nm process has been able to introduce EUV faster and the yield rate has been improved as expected. Compared with the 7nm process, the 5nm chip density has increased by 80%, which can reduce power consumption by 15% at the same computing performance and increase computing performance by 30% at the same power consumption. Moreover, the 5nm process also uses the ultra-low power consumption design of extremely low threshold voltage (ELVT) transistors for the first time, which can still increase computing performance by 25% under ELVT computing.


Furthermore, TSMC will launch an enhanced version of 5nm (N5+) one year after 5nm mass production. Compared with the 5nm process, it can further increase computing performance by 7% at the same power consumption, or reduce power consumption by 15% at the same computing performance. The N5+ process will start trial production in the first quarter of 2020 and enter mass production in 2021.




TSMC will also launch 3D chip packaging processes in the 5nm process generation to meet customer needs for high-performance computing and 5G applications, including wafer stacking of wafers with the same chip size and process, and system integration single-chip packaging with chips stacked on wafers. The industry is optimistic about TSMC's 3D chip stacking packaging solution, which can integrate multiple closely adjacent heterogeneous chiplets and provide better system performance.


According to legal speculation, TSMC will regard 5nm as a major node after 7nm, which will have significant benefits in terms of chip density, computing performance, and reducing power consumption. Major customers including Apple, Huawei HiSilicon, AMD, Xilinx, NVIDIA, Broadcom, etc. will entrust TSMC to mass-produce 5nm chips or processors. As for Qualcomm's 5nm orders, it is expected that they will also return to TSMC for wafer production.


Source: Content from "China Business Times", thank you.


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