P-Channel JFET Switch
LLC
J174 – J177 / SST174 – SST177
FEATURES
ABSOLUTE MAXIMUM RATINGS
(T
A
= 25
o
C unless otherwise specified)
Gate-Drain or Gate-Source Voltage . . . . . . . . . . . . . . . . . 30V
Gate Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA
Storage Temperature Range . . . . . . . . . . . . . -55
o
C to +150
o
C
Operating Temperature Range . . . . . . . . . . . -55
o
C to +135
o
C
Lead Temperature (Soldering, 10sec) . . . . . . . . . . . . . . 300
o
C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350mW
Derate above 25
o
C . . . . . . . . . . . . . . . . . . . . . . . 3.3mW/
o
C
NOTE:
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. These are
stress ratings only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
•
Low Insertion Loss
•
No Offset or Error Generated By Closed Switch
-
Purely Resistive
-
High Isolation Resistance From Driver
•
Short Sample and Hold Aperture Time
•
Fast Switching
•
Analog Switches
•
Choppers
•
Commutators
PIN CONFIGURATION
APPLICATIONS
ORDERING INFORMATION
Part
SOT-23
G
TO-92
Package
Temperature Range
J174-J177
Plastic TO-92
-55
o
C to +135
o
C
SST174-SST177
Plastic SOT-23
-55
o
C to +135
o
C
For Sorted Chips in Carriers see 2N5114 series.
D
S
S
D G
PRODUCT MARKING (SOT-23)
SST174
P04
P05
P06
P07
SST175
SST176
SST177
5508
CALOGIC LLC,237 WHITNEY PLACE, FREMONT, CA 94539, 510-656-2900 PHONE, 510-651-1076 FAX
DS040 REV A
LLC
ELECTRICAL CHARACTERISTICS
(T
A
= 25
o
C unless otherwise specified)
SYMBOL PARAMETER
Gate Reverse
Current
(Note 1)
Gate Source
Cutoff Voltage
Gate Source
Breakdown
Voltage
Drain
Saturation
Current
(Note 2)
Drain Cutoff
Current
(Note 1)
Drain-Source
ON Resistance
Drain-Gate
OFF
Capacitance
Source-Gate
OFF
Capacitance
Drain-Gate
Plus Source
Gate ON
Capacitance
Turn On Delay
Time
Rise Time
Turn Off Delay
Time
Fall Time
5.5
5
J174
J175
J176
J177
UNITS
TEST CONDITIONS
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
I
GSS
1
1
1
1
nA
V
DS
= 0, V
GS
= 20V
V
GS(off)
10
3
6
1
4
0.8
2.25
V
V
DS
= -15V, I
D
= -10nA
BV
GSS
30
30
30
30
V
DS
= 0, I
G
= 1µA
I
DSS
-20
-135 -7
-70
-2
-35 -1.5
-20
mA
V
DS
= -15V, V
GS
= 0
I
D(off)
-1
-1
-1
-1
nA
Ω
V
DS
= -15V, V
GS
= 10V
r
DS(on)
85
125
250
300
V
GS
= 0, V
DS
= -0.1V
C
dg(off)
5.5
5.5
5.5
V
DS
= 0,
V
GS
= 10V
C
sg(off)
5.5
5.5
5.5
5.5
pF
f = 1MHz (Note 3)
C
dg(on)
+ C
sg(on)
32
32
32
32
V
DS
= V
GS
= 0
t
d(on)
t
r
t
d(off)
t
f
2
5
5
10
5
10
10
20
15
20
15
20
20
25
20
25
ns
Switching Time Test Conditions
(Note 3)
J174
J175
J176
V
DD
-10V
-6V
-6V
V
GS(off)
12V
8V
3V
R
L
560Ω 12kΩ 5.6kΩ
V
GS(on)
0V
0V
0V
J177
-6V
3V
10kΩ
0V
NOTES: 1.
Approximately doubles for every 10
o
C increase in T
A
.
2.
Pulse test duration -300µs; duty cycle
≤3%.
3.
For design reference only, not 100% tested.
CALOGIC LLC, 237 WHITNEY PLACE, FREMONT, CA 94539, 510-656-2900 PHONE, 510-651-1076 FAX
DS040 REV A