If electronic engineers change these 29 habits, you will be a master!

Phenomenon 1: The resistance value of these pull-up/pull-down resistors does not matter much, just choose an integer of 5K

Comments: There is no 5K resistance value on the market. The closest one is 4.99K (1% accuracy), followed by 5.1K (5% accuracy), which cost 4 times and 2 times higher than 4.7K with 20% accuracy. The resistance values ​​of 20% accuracy resistors are only 1, 1.5, 2.2, 3.3, 4.7, 6.8 (including integer multiples of 10); similarly, the capacitors with 20% accuracy also have the above values. If you choose other values, you must use higher accuracy, which will double the cost without any benefits.

Phenomenon 2: What color should I choose for the indicator light on the panel? I think blue is more special, so I'll choose it.

Comments: Other colors such as red, green, yellow, orange, etc., regardless of size (less than 5MM) and packaging, have been mature for decades, and the price is generally less than 50 cents, while blue is something that was invented in the past three or four years. The technical maturity and supply stability are poor, but the price is four or five times more expensive. At present, blue indicator lights are only used in situations where other colors cannot be used, such as displaying video signals.

Phenomenon 3: This logic can be built with 74XX gate circuits, but it is too rustic. It is better to use CPLD, which looks more advanced.

Comment: The gate circuit of 74XX is only a few cents, while CPLD is at least dozens of dollars. (Although GAL/PAL is only a few dollars, the company does not recommend its use.) Not only does the cost increase by N times, but it also adds several times the work of production and documentation.

Phenomenon 4: Our system requirements are so high that all chips including MEM, CPU, FPGA, etc. must be the fastest

Comment: In a high-speed system, not every part works at high speed. Every time the device speed increases by one level, the price almost doubles, and it also has a great negative impact on signal integrity issues.

Phenomenon 5: The PCB design requirements of this board are not high, so just use thinner wires and automatically lay them out.

Comment: Automatic routing will inevitably occupy a larger PCB area and produce many times more vias than manual routing. In large-volume products, the factors that PCB manufacturers consider when reducing prices, in addition to business factors, are line width and the number of vias. They affect the PCB yield and the number of drill bits consumed, respectively, saving suppliers' costs and finding a reason for price cuts.

Phenomenon 6: As long as the program is stable, it doesn’t matter if the code is longer or the efficiency is lower.

Comment: CPU speed and memory space are bought with money. If you spend a few more days writing code to improve program efficiency, the cost saved by reducing CPU frequency and memory capacity is definitely worth it. CPLD/FPGA design is similar.

Phenomenon 1: Our system is powered by 220V, so we don’t have to worry about power consumption

Comments: Low power consumption design is not only for saving electricity, but also has the advantages of reducing the cost of power modules and cooling systems, and reducing electromagnetic radiation and thermal noise interference due to the reduction of current. As the temperature of the equipment decreases, the life of the device is correspondingly extended (the life of semiconductor devices is shortened by half for every 10 degrees increase in the operating temperature of the semiconductor device).

Phenomenon 2: These bus signals are pulled up with resistors, and I feel more assured.

Comments: There are many reasons why signals need to be pulled up and down, but not all of them need to be pulled up. When the pull-up and pull-down resistors pull a simple input signal, the current is less than tens of microamperes, but when pulling a driven signal, the current will reach the milliampere level. Today's systems often have 32 bits of address data each, and there may also be 244/245 isolated buses and other signals. If all are pulled up, several watts of power consumption will be consumed by these resistors (don't use the concept of 80 cents per kilowatt-hour to treat these few watts of power consumption).

Phenomenon 3: How to deal with these unused I/O ports of CPU and FPGA? Leave them empty for now and we will deal with them later.

Comment: If an unused I/O port is left floating, a little interference from the outside world may cause the input signal to oscillate repeatedly, and the power consumption of MOS devices basically depends on the number of gate circuit flips. If it is pulled up, each pin will also have a micro-ampere current, so the best way is to set it as an output (of course, other driven signals cannot be connected outside)

Phenomenon 4: This FPGA still has so many gates left to use, so you can use them to your heart's content

Comment: The power consumption of FGPA is proportional to the number of flip-flops used and the number of flip-flops they flip, so the power consumption of the same model of FPGA at different times in different circuits may differ by 100 times. Minimizing the number of high-speed flip-flops is the fundamental way to reduce FPGA power consumption.

Phenomenon 5: The power consumption of these small chips is very low, so there is no need to consider

Comment: It is difficult to determine the power consumption of chips with less complex internal components. It is mainly determined by the current on the pins. An ABT16244 consumes less than 1 mA without a load, but its indicator is that each pin can drive a 60 mA load (such as matching a resistor of several tens of ohms), that is, the maximum power consumption at full load can reach 60*16=960mA. Of course, the power supply current is so large that the heat falls on the load.

Phenomenon 6: The memory has so many control signals, but my board only needs to use OE and WE signals, and the chip select should be grounded, so that the data can come out much faster during the read operation.

Comment: The power consumption of most memories when chip select is valid (regardless of OE and WE) will be more than 100 times greater than when chip select is invalid, so CS should be used to control the chip as much as possible, and the width of the chip select pulse should be shortened as much as possible while meeting other requirements.

Phenomenon 7: Why do these signals have overshoot? As long as the matching is good, it can be eliminated

Comments: Except for a few specific signals (such as 100BASE-T and CML), all signals have overshoot. As long as it is not too large, it is not necessary to match them. Even if they are matched, they do not have to be matched to the best. For example, the output impedance of TTL is less than 50 ohms, and some are even 20 ohms. If such a large matching resistor is used, the current will be very large, and the power consumption will be unacceptable. In addition, the signal amplitude will be too small to be used. Besides, the output impedance of general signals is not the same when outputting high level and low level, so there is no way to achieve complete matching. Therefore, for the matching of TTL, LVDS, 422 and other signals, it is sufficient to make the overshoot acceptable.

Phenomenon 8: Reducing power consumption is the job of hardware personnel, not software

Comment: Hardware is just a stage, but software is the performer. Access to almost every chip and flipping of every signal on the bus are controlled by software. If the software can reduce the number of accesses to external memory (using more register variables, using more internal CACHE, etc.), respond to interrupts in a timely manner (interrupts are often valid at low levels and have pull-up resistors) and other specific measures for specific boards, it will make a great contribution to reducing power consumption.

Phenomenon 1: This CPU with a main frequency of 100M can only process 70%, and it will be fine if you change it to a CPU with a main frequency of 200M

Comment: The processing power of a system involves a variety of factors. In the communication business, the bottleneck is usually the memory. No matter how fast the CPU is, it will be in vain if the external access is not fast enough.

Phenomenon 2: CPU should be faster if it uses a larger cache

Comment: The increase of CACHE does not necessarily lead to an improvement in system performance. In some cases, closing the CACHE is faster than using it. The reason is that the data moved to the CACHE must be reused many times to improve system efficiency. Therefore, in communication systems, only the instruction CACHE is generally turned on. Even if the data CACHE is turned on, it is limited to part of the storage space, such as the stack. At the same time, it also requires program design to take into account the capacity and block size of the CACHE, which involves the length of the key code loop body and the jump range. If a loop is just a little bit larger than the CACHE and it is repeatedly looped, it will be terrible.

Phenomenon 3: For so many tasks, should we use interrupt or query? Interrupt is faster.

Comments: Interrupts are highly real-time, but not necessarily fast. If there are too many interrupt tasks, the system will crash soon if one task is not exited and the next one comes one after another. If there are many tasks but they are very frequent, a lot of CPU energy will be used for the overhead of entering and exiting interrupts, and the system efficiency is extremely low. If the query method is used instead, the efficiency can be greatly improved, but the query sometimes cannot meet the real-time requirements, so the best way is to query in the interrupt, that is, to process all the accumulated tasks once the interrupt is entered and then exit.

Phenomenon 4: The timing of the memory interface is the manufacturer's default configuration and does not need to be modified

Comments: The default values ​​of the memory interface settings in BSP are all set according to the most conservative parameters. In actual applications, they should be reasonably adjusted in combination with parameters such as bus operating frequency and waiting cycle. Sometimes, lowering the frequency can improve efficiency. For example, if the RAM access cycle is 70ns and the bus frequency is 40M, set the access time to 3 cycles, that is, 75ns; if the bus frequency is 50M, it must be set to 4 cycles, but the actual access time is slowed down to 80ns.

Phenomenon 5: If one CPU cannot handle the data, use two distributed processors to double the processing power.

Comment: For moving bricks, two people should be twice as efficient as one person; for painting, one more person can only make things worse. You need to have a better understanding of the business before deciding how many CPUs to use, and try to reduce the cost of coordination between the two CPUs, so that 1+1 is as close to 2 as possible, and never less than 1.

Phenomenon 6: This CPU has a DMA module, so it is definitely faster to use it to move data

Comments: Real DMA is when the hardware seizes the bus and starts the devices at both ends at the same time, reading on one side and writing on the other side in one cycle. However, many DMAs embedded in CPUs are just simulations. Before starting each DMA, a lot of preparation work must be done (setting the starting address and length, etc.). During transmission, the data is often read into the chip for temporary storage first, and then written out. That is, it takes two clock cycles to move data once, which is faster than software (no need to fetch instructions, no extra work such as loop jumps, etc.). However, if only a few bytes are moved at a time, a lot of preparation work must be done, which generally involves function calls, and the efficiency is not high. Therefore, this type of DMA is only applicable to large data blocks.

Phenomenon 1: These signals have been simulated and there is absolutely no problem

Comments: It is impossible for a simulation model to be exactly the same as the real object. Even the real objects processed in different batches are different, let alone the model. In addition, the actual situation varies greatly, and simulation cannot exhaust all possibilities, especially crosstalk. There was a lesson that a certain board was prone to packet loss with only a certain length of packets. The final reason was that the value of the length field was 0xFF. When this data appeared on the bus, it interfered with the adjacent WE signal, resulting in failure to write into RAM. Other data will also interfere with WE, but the interference is within an acceptable range. However, when the 8-bit bus changes from 0 to 1 at the same time, the nearby signals cannot withstand it. The conclusion is that the simulation results are for reference only, and sufficient margin should be left.

Phenomenon 2: The 100M data bus should be considered a high-frequency signal, but the clock signal frequency is only 8K, which is not a big problem.

Comment: The value of the data bus is generally sampled by a certain edge of the control signal or the clock signal. As long as sufficient setup time and hold time are maintained for this edge, interference or overshoot outside this range will not have much impact (of course, the overshoot should not exceed the maximum voltage value that the chip can withstand). However, no matter how low the frequency of the clock signal is (in fact, the spectrum range is very wide), its edge is the key. Its monotonicity must be guaranteed, and the transition time must be within a certain range.

Phenomenon 3: Since it is a digital signal, the steeper the edge, the better

Comment: The steeper the edge, the wider the spectrum range and the greater the energy of the high-frequency part; the higher the frequency signal, the easier it is to radiate (for example, microwave radio stations can be made into mobile phones, while many countries cannot make long-wave radio stations), and the easier it is to interfere with other signals, while the transmission quality on the wire becomes worse. Therefore, try to use low-speed chips if possible.

Phenomenon 4: To ensure a clean power supply, the more decoupling capacitors the better

Comments: In general, the more decoupling capacitors there are, the more stable the power supply will be. However, too many decoupling capacitors also have disadvantages: wasted cost, difficult wiring, too much power-on impact current, etc. The key to the design of decoupling capacitors is to choose the right capacity and put them in the right place. General chip manuals have references for the design of decoupling capacitors, so it is best to follow the manual.

Phenomenon 5: Signal matching is really troublesome, how can we match it well?

Comments: The general principle is that when the transmission time of the signal on the wire exceeds its jump time, the reflection of the signal becomes important. The reason for the reflection of the signal is the uneven impedance of the line. The purpose of matching is to make the impedance of the driver end, the load end and the transmission line close, but whether the matching is good or not is also closely related to the topological structure of the signal line on the PCB. A branch, a via, a corner, a connector, and the change of the distance between different positions and the ground line on the transmission line will cause the impedance to change, and these factors will make the reflected waveform extremely complex and difficult to match. Therefore, high-speed signals only use point-to-point methods to minimize vias, corners and other problems.

Phenomenon 1: This board has been produced in small batches, and no problems were found after a long period of testing

Comments: Hardware design and chip application must comply with relevant specifications, especially all parameters mentioned in the chip manual (voltage resistance, I/O level range, current, timing, temperature PCB wiring, power quality, etc.), which cannot be verified by experiments alone. Many of our products have had painful lessons. After the product was sold for one or two years, the IC manufacturer changed the production line, and our board stopped turning. The reason was that the chip parameters of the manufacturer changed a little, but did not exceed the range of the manual. If you take the manual as the standard, then you are not afraid of any changes. If the parameters become beyond the range of the manual, you can still claim compensation from him (if your board can still turn at this time, then your reliability is even better).

Phenomenon 2: This part of the circuit will not have any problems as long as the software is designed in this way

Comment: Many electrical characteristics of hardware are directly controlled by software, but software often has unexpected problems. It is unpredictable what operations will be performed after the program runs wild. Designers should ensure that no matter what operations the software performs, the hardware should not be permanently damaged in a short period of time.

Phenomenon 3: If a user makes an error in operation, you can’t blame me

Comments: It is right to require users to strictly follow the manual, but users are human and they make mistakes sometimes. You cannot say that the system crashes if you touch a wrong key or burn the board if you plug in a wrong plug. Therefore, you must protect users from various mistakes they may make.

Phenomenon 4: The reason why this board is broken is that there is a problem with the board on the other end, and it is not my responsibility

Comments: There should be sufficient compatibility for various external hardware interfaces. You cannot stop working just because the signal from the other party is abnormal. The abnormality should only affect the functions related to it, while other functions should be able to work normally. It should not go on strike completely or even be permanently damaged. Once the interface is restored, you should also immediately return to normal.