High-Speed ​​I/O Circuit IBIS/AMI Modeling and Verification - Training Course

All relevant units:

Co-organized by Shanghai Lefu Education Technology Co., Ltd. and Shanghai Zhangjiang Innovation Institute "IBIS/AMI Modeling and Verification of High-Speed ​​I/O Circuits " Training course, specially invited Cadence Electronic Technology (Shanghai) Co., Ltd. (Cadence) Chief Engineer - Qin Zuli and global IBIS/AMI modeling expert, IBIS Technology Forum Vice Chairman, IO Methodology Inc. founder, Mr. Lance Wang, two industry IBIS modeling experts, served as instructors for this course.

This carefully designed training course combines theory and practice, and aims to provide a set of systematic IBIS modeling and verification methods and processes for IBIS modeling and verification engineers, system hardware engineers, signal integrity engineers, and other IBIS model creators, users, and application engineers in electronic product system manufacturers, integrated circuits, chip design companies, universities and research institutes, high-speed I/O and IP suppliers, etc., combined with 10 current mainstream high-speed parallel I/O (DDRn/LPDDRn/eMMC /SDIO /GPIO), The IBIS modeling and verification cases of serial I/O (MIPI/HDMI/LVDS/USBx/SerDes) interfaces enable students to quickly master the principles and interface specifications of mainstream high-speed I/O circuits, SPICE netlist editing and debugging, IBIS syntax and specifications, RLC parameter extraction methods of mainstream chip packages (QFP/QFN/LGA/FBGA/PBGA/FCCSP/FCBGA/FOWLP/SiP/PoP, etc.), the two most commonly used IBIS modeling EDA software in the industry - modeling processes and methods based on table-based configuration and GUI circuit graphics, creation of full-chip-level IBIS models, IBIS model quality checklist and accuracy verification, and the principles and modeling methods of IBIS-AMI algorithm interface models.

Through in-depth discussions on these technical issues and applicable skills training, it will help to quickly improve the IBIS modeling and application capabilities of engineers or related technical personnel, ensure the accuracy and quality of the IBIS model, so as to facilitate integrated circuit design companies and electronic product system developers to more accurately verify and predict the signal integrity and power integrity of high-speed interfaces, optimize and modify I/O design or chip design based on the results of simulation analysis before the chip Tape-out, ensure the electrical performance and reliability of the final electronic product, accelerate the listing of products, and enhance the competitiveness of corporate products. At the same time, the organizer will establish an IBIS modeling technology exchange group to promote better cooperation and communication between electronic product system manufacturers, integrated circuit and semiconductor industry ecosystem peers.

The relevant matters are now notified as follows:

organizer

Shanghai Lefu Education Technology Co., Ltd.

Shanghai Zhangjiang Innovation Institute

Participant

The course is aimed at senior executives, technical supervisors, I/O design engineers, circuit engineers, signal integrity engineers, system hardware designers, packaging design engineers, project supervisors, business managers, etc. from relevant electronic information and integrated circuit enterprises (including integrated circuit chip design companies, electronic product system manufacturers, universities and research institutes, high-speed I/O and IP suppliers, IC wafer foundries, packaging and assembly plants, and related EDA software companies), as well as researchers from scientific research institutions, university professors, and relevant industry market researchers and VC investors.

The course PPT is in Chinese and English, and the lectures are in Chinese.

class schedule

Training time: April 8-9, 2016 (2 days)

Training location: Conference Hall on the second floor of ZTE Hetai Hotel

No. 866, Keyuan Road, Zhangjiang Hi-Tech Park, Pudong New Area, Shanghai

curriculum structure:

1) Reason Theory and Methodology Concentrated Lectures :

On April 8-9, 2016 (two days in total), the teacher will systematically teach the methodology and process of IBIS modeling and verification, and demonstrate high-speed parallel and serial interface IBIS modeling and verification cases. .

2) Class Post-cloud project case training :

From April 15 to July 15, 2016 (three months in total), each student was provided with a cloud server login account after class. According to the project training manual, EDA software (based on table configuration, GUI circuit graphics, package RLC extraction and SPICE simulation engine) and project data database, the students completed the modeling and verification of 10 high-speed parallel interface and serial interface project cases. The instructor provided technical support and answered questions.

3) After the training course, Shanghai Lefu Education will issue the "High-Speed ​​I/O Circuit IBIS/AMI Modeling and Verification" skill certificate.

Participants of the training may be recommended to participate in the national "Software and Integrated Circuit Talent Training Program" selection.

training fees

The training fee for this course is RMB 4,000 per person (including teaching fee, venue fee, materials fee, lunch/dinner during the training period, certificate and souvenirs). Students are responsible for their own transportation, food and accommodation (relevant agreement hotel information will be provided for selection before the course starts). Please remit the training fee to the following bank account before March 30, 2016.

Account name: Shanghai Lefu Education Technology Co., Ltd.

Bank of account: CITIC Bank Shanghai Zhangjiang Branch

Account number: 8110201013300125043

ways of registration

After receiving the notice, please actively select personnel to participate.

The application deadline is March 30, 2016

Contact: Ban Keke

Add QQ: 416000888 to get the receipt form

Tel: 13174190103

Email : 416000888@qq.com

appendix:

1. Course Introduction

2. Course Outline

3. Expert Profile

Appendix 1: Course Introduction

The IBIS (Input/Output Buffer Information Specification) model is a method for quickly and accurately modeling I/O circuits based on current-voltage (IV) curves and voltage-time (VT) curves to describe the input/output behavior characteristics of the I/O Buffer. Its purpose is to provide a standard method for the interaction of chip I/O circuit models between integrated circuit chip design manufacturers and electronic system design manufacturers.

When using SPICE models for PCB board-level and system-level signal integrity (SI) analysis, integrated circuit designers and manufacturers are required to provide transistor-level circuit models and process parameters that can accurately describe the IC I/O unit subcircuits in detail. Since these data are usually the intellectual property and confidentiality of designers and manufacturers, only very few semiconductor design manufacturers will provide corresponding encrypted SPICE models while providing chip products. When some semiconductor design manufacturers provide SPICE models to the outside world, they often "clean up" some parts involving intellectual property rights, which will also lead to inaccurate simulation results. In addition, when using SPICE models for SI analysis of high-speed serial and parallel bus interfaces, the simulation time is often very long (several days or more than a week). Especially for complex PCB board-level systems, SPICE simulation also consumes up to hundreds of GB or even TB of computer memory resources. It is basically impossible to obtain preliminary simulation results in a short time (several hours or 1-2 days). SPICE simulation also places stringent requirements on computer hardware resources.

IBIS is a behavioral model that is not defined based on the structure of the component to be simulated, but on the behavior of the component. The IBIS model does not describe the specific structure of the circuit, but only uses I/V and V/T tables to describe the characteristics of the I/O units and pins of the digital integrated circuit. Semiconductor manufacturers can easily provide this model to customers without exposing their intellectual property rights. Due to the convenience, speed, and necessary accuracy of the IBIS model, most chip design manufacturers in the industry have realized the importance of the IBIS model, and provide the IBIS model as part of the chip standard delivery document, together with the chip data sheet, application notes, system design guide, etc., to system manufacturer customers for acceptance analysis of electrical performance indicators such as signal integrity and power integrity of the customer's own board-level system.

This training course is aimed at the current high-speed design field I/O design engineers, circuit engineers, signal integrity engineers, system hardware designers and project managers who are faced with the following problems in the development and verification of high-speed interfaces: how to use the correct method to create high-precision, high-quality IBIS models, how to verify IBIS models (monotonousness of I/V and V/t curves, Duty Cycle, Overclocking, etc.), the application and model selection of IBIS in actual PCB board-level systems, missing IBIS model information, unclear keyword definitions in the model, and difficulty in accepting signal eye diagram quality. In a step-by-step approach that combines theory with practice, the author discusses and shares the principle implementation, specification definition, creation principle and verification method of behavioral-level IBIS models of mainstream I/O interfaces, as well as the extraction method of full-chip and full-package IBIS model files. The author also comprehensively explains the latest IBIS specification definition, IBIS-AMI algorithm model interface and mainstream AMI algorithm principles, and demonstrates the creation process of IBIS models one by one through multiple actual project cases, helping students quickly master the IBIS modeling technology of various mainstream I/O interfaces. Finally, by sharing the engineering problems often encountered in the IBIS modeling process and the corresponding solutions and solutions, the student modeling skills are further improved, so as to ensure that the accuracy and quality of the provided IBIS model meet the requirements of high-speed interface system verification in actual work.

IBIS (I/O Buffer Information Specification),

as an international behavioral buffer model

standard, is popular to be used for High-Speed

digital system designs since 90's. It is not only

provided a standard portability format for cross

EDA simulation tools but also performance, sec

-urity and accuracy for computing, network and

mobile device designs.

This class will cover some practical topics

for IBIS model development, validation and

simulation. It includes IBIS Standard basics in

-troduction, How to develop high-accuracy,

high-quality IBIS buffer models, IBIS buffer mo

-del validation techniques as well as IBIS AMI

model introductions.

In this class, we will also go over the IBIS

simulation settings as well as the live demo us

-ing leading IBIS development tool for IBIS de

-velopment.

Appendix 3: Introduction of lecturers

1 Qin Zuli

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Mr. Qin Zuli joined Sigrity, a leading manufacturer of high-speed design signal and power integrity EDA tools, in October 2010 (acquired by Cadence Design Systems in July 2012). He served as a senior product engineer and application engineer, responsible for the promotion and support of key projects for domestic core customers (such as HiSilicon, Spreadtrum, Changdian, VAS, etc.), and undertook multiple design service projects with fabless design companies (including SI/PI acceptance analysis of a tablet chip DDR3 interface, timing acceptance and packaging optimization analysis of high-power server-level CPU chips, reference design kit development for a mobile phone communication solution, AMI algorithm model development for USB3.0 interface, etc.), and participated in the development and verification of Cadence's I/O transistor circuit to IBIS model conversion tool. He is currently responsible for helping core customers build a full-link (chip-package-system) power integrity analysis process and create AMI algorithm models and full-chip IBIS models for high-speed SerDes interfaces. In the past 4 years, he has provided technical support for the creation and verification of IBIS models for more than 100 domestic and foreign customers, and has accumulated rich modeling cases and experience.

Mr. Qin Zuli has more than 10 years of work experience in semiconductor and high-speed design SI/PI simulation analysis. He has a solid foundation in electromagnetic field theory, signal integrity and power integrity, and has rich experience in modeling and simulation from chip to package and system, as well as Spice netlist editing and debugging analysis. Before joining Sigrity, Mr. Qin Zuli worked as a senior R&D for many years at Apache Design Solutions and ASML, responsible for the development of chip-level IR-Drop/SSO/EMI simulation analysis and lithography process simulation analysis software. He has a deep understanding of chip design and process flow, advanced packaging design optimization and process flow, signal integrity acceptance analysis of high-speed serial and parallel interfaces of PCB board-level systems, power integrity analysis and optimization, etc. Mr. Qin Zuli has also been a guest speaker at the IBIS forum many times to share the latest achievements of Sigrity/Cadence in the field of IBIS technology evolution.

Mr. Qin Zuli graduated from the School of Information Science and Technology of Zhejiang University in 2005 with a master's degree. As a core editor of the book "Cadence High-Speed ​​Circuit Design", he used easy-to-understand language and combined theory with practice to explain the analysis methods and engineering experience of full-link power integrity, which won unanimous praise from readers.

2 Wang Liqun

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Mr. Wang Liqun is a global IBIS/AMI modeling expert and the founder, chairman and CEO of IO Methodology Inc. IO Methodology is the world's first EDA company to develop the most convenient and easy-to-use IBIS modeling and verification tools based on GUI interface. Famous semiconductor companies around the world include: Samsung Electronics (Sumsung), Texas Instruments (TI), Micron Electronics (Micron), Lattice (Lattice), Atmel, Hisilicon (Hisilicon), Sem tech, Spreadtrum (Spreadtrum), Novatek, HiMax, Winbond, etc. are all customers of IO Methodology products and users of IBIS modeling methods; in addition, IO Methodology is also a supplier of IBIS modeling services to well-known companies such as ST Microelectronics and Aragio Solutions .

Since 2005, Mr. Wang Liqun has been the Vice Chairman of the IBIS Technology Forum, responsible for hosting and coordinating international IBIS conferences and promoting the development of IBIS standards and related technical applications. Con

, More than 20 technical papers and presentations on IBIS modeling and verification were presented at IEEE, SPI, and JEITA international technical conferences. In 2006, he was one of the initiators and proposed the IBIS AMI model specification.

Before founding IO Methodology, Mr. Wang Liqun worked at Cadence in the United States for 7 years from 2000 to 2007. He was a modeling expert and product manager for Cadence PCB SI products. He also worked as a system design engineer at GSI Lumonics and Connection Technology, and as a technical service manager at Motorola China.

Mr. Wang Liqun graduated from ShanghaiTech University in 1985 with a bachelor's degree in microwave and electromagnetic fields. After immigrating to the United States in 1995, he participated in computer engineering and MBA program courses at Massachusetts Institute of Technology (MIT), Boston University (BU) and New York Institute of Technology (NYPI) and obtained a master's degree.