CMOS revolution

Latest update time：2024-01-21

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A common framework and continued miniaturization are keys to CMOS's success. Recently, however, CMOS has faced unprecedented scaling and cost challenges as computing demands have surged across a variety of architectures and applications. This requires us to reimagine existing paradigms.

CMOS technology has revolutionized the electronics industry by balancing performance, energy efficiency and economics. The system-on-a-chip (SoC) paradigm allows for a common approach to driving increasingly complex systems, integrating an increasing number of transistors on a single chip. This also enables high-volume and low-cost production, increasing the affordability of electronics, as predicted by the late Gordon Moore more than half a century ago.

Moore said the number of transistors on a semiconductor chip is doubling every two years, a trend that will drive the development of increasingly powerful and efficient electronic devices. In short, you can make things better by making them smaller.

The enormous focus on miniaturization and universal design has been at the core of CMOS's huge success over the past few decades, but it is now approaching its physical limits.

CMOS scaling hits multiple roadblocks

While the SoC approach provides maximum energy efficiency, it forces system architects to accumulate a large amount of complex functionality within the CMOS platform. The optimization of multi-core architectures born in the 2000s has led to the rise of multiple computing engines, from the original CPU to GPU segmentation, to different power-optimized processors, to different types of accelerators. Memory subsystems within SoCs have also diversified extensively over the years, resulting in complex hierarchies and various access mechanisms.

The driving force behind this continuous optimization is the need to optimize a computing system based on the type of tasks or workloads it must perform, each of which is highly specific to the target application. It is worth noting that this evolution can even be achieved within a single technology platform, and as it currently stands, there are several important obstacles hindering its further development:

We are witnessing huge advances in micro-bump pitch scaling and hybrid bonding-driven chip-to-chip electrical interconnects, which allow fine-grained partitioning of SoC functionality. Advances in silicon photonics-based optical interconnects and 3D interconnects enable co-packaging to deliver high-bandwidth, low-power optical connections at shorter lengths. This begs the question: whether the SoC approach still maintains its original energy efficiency advantages. Splitting into multiple chips can bring huge benefits in terms of cost and performance optimization.

The diversity of applications requires advanced technologies to push the boundaries of computing performance, pushing CMOS to the limits of what it can offer as a general-purpose platform. Designers now need to work around the limitations of a single platform, which sometimes results in significant inefficiencies.

A holistic scaling solution for the entire CMOS platform is becoming increasingly difficult to achieve. For example, 2nm nanosheet technology will enable traditional thick oxide IO circuits to be moved out of SoCs. SRAM does not scale as well as logic, and power in the SoC needs to be distributed through the backside interconnect network as frontside interconnect resistance can become prohibitive.

Node-to-node performance improvements in CMOS are also significantly reduced because transistor RC parasitics grow faster than drive strength. This situation arises as the design and wafer costs of advanced CMOS increase significantly due to the complexity of design rules and process integration.

From universal to lottery

Creative combinations give rise to innovative solutions in an interesting context of constantly changing technology and product requirements. The Apple M1 Ultra, for example, essentially stitches two chips together via a silicon bridge, creating a hybrid SoC with unprecedented performance and functionality. AMD increased memory capacity by 3D stacking SRAM chips on top of the original processor SoC. In the field of artificial intelligence, super scale-out processing systems such as all-wafer Cerebras' WSE-2 and Nvidia's large GPU chip H100 combined with HBM DRAM are pushing the boundaries of deep learning computing.

The above example illustrates how technology development can be pushed to extremes based on the specific needs of a given application space. At the same time, emerging applications such as augmented and virtual reality, 6G wireless and autonomous vehicles will require dramatic performance improvements and power consumption reductions. Workloads and operating conditions will further increase the diversity of implementations supported by CMOS, forcing more suboptimal compromises.

In other words, we are witnessing CMOS failing to fulfill its powerful role as a general-purpose technology. Instead, we end up with a situation where the success of an application will depend on how well the available CMOS meets its specific boundary conditions. Sara Hooker coined the "hardware lottery" to suggest that hardware determines which research ideas succeed or fail.

Collaborative optimization systems and technologies

When your only tool is a hammer, it's easy to treat every problem like a nail. The only way to solve this dilemma is to expand your toolbox. In other words, we need a more general technology platform because the energy, cost, temperature, power density, memory capacity, speed, etc. constraints of mobile chipsets are very different from those of HPC or VR systems.

That’s why we envision a new paradigm driven by System Technology Co-Optimization (STCO): CMOS 2.0. STCO involves system designers working closely with technical teams to identify the most appropriate options, rather than relying on off-the-shelf expansion options. Technical teams also need to understand specific system specifications when developing next-generation products. The diversity of applications, workloads, and system constraints will require a broader selection of technologies.

It requires rethinking technology platforms to meet the needs of a variety of systems and applications. CMOS 2.0 accomplishes this by enabling custom chips that are built with intelligent partitioning of various functions in multiple 3D stacked layers (Figure 1).

CMOS2.0 has the same “look and feel” as the classic CMOS platform

Unlike the heterogeneous systems we see today, where hybrid bonding solves memory limitations, active interposers solve bandwidth limitations, and backside power distribution networks solve power consumption issues, CMOS 2.0 A more revolutionary approach was taken by introducing heterogeneity internally. It will have the same "look and feel" as the classic CMOS platform while providing more features for system optimization. The dense logic layer will represent the majority of the cost and will still require scaling. However, other scaling restrictions have now been physically removed to other layers.

Best of both worlds

CMOS 2.0 will leverage existing and new advanced 2.5D and 3D interconnect technologies such as dense-pitch copper hybrid bonding, dielectric bonding, chiplet integration, backside processing of wafers, and sequential 3D integration involving heterogeneous layer transfer. It will allow for the high interconnect granularity of SoCs and the high-tech heterogeneity offered by systems within packages, fundamentally lifting the limitations of traditional CMOS.

CMOS 2.0 will allow the use of low-capacitance, low-drive transistors to drive short-range interconnects, while utilizing high-drive transistors in separate layers to drive long-range interconnects. New embedded memory can be introduced as a separate layer in the cache hierarchy. It also enables extreme BEOL pitch patterns for scaling without being limited by supply voltage drop. Introducing non-silicon devices (such as 2D materials), new embedded memories (such as MRAM or deposited oxide semiconductors) will become easier because they do not need to meet common CMOS specifications. To designers, the CMOS 2.0 platform feels like traditional CMOS, but with a significantly expanded and more versatile toolbox.

While dimensional scaling is no longer the only answer to driving computing scaling, CMOS 2.0 will not eliminate the need for increased density. However, the scaling issue must be addressed in a more comprehensive way, as the answer will vary depending on the application. High-density logic will optimize performance per watt, while high-drive logic maintains bandwidth and performance in critical paths. Less scalable devices, such as dense logic thick oxide IO, power switches, analog or MIMCAP, can now be integrated in separate layers using more cost-effective technology nodes. Removing all necessary but non-scalable SoC parts also opens the door to a new class of devices.

The revolution has begun

The backside power distribution network is the first sign that we are entering the new CMOS 2.0 era. All major foundries have announced that they will move to integrated chips equipped with power distribution systems on the backside of the wafer, which is becoming increasingly important for enabling high-performance and energy-efficient electronic devices. The use of backside wafer processing provides opportunities to integrate devices such as power switches, migrate global clock routing from the frontside, or add new system functionality.

Arguably, this paradigm shift offers a more complex technological reality. How fast are EDA tools evolving? Will the cost and complexity of zoning become prohibitive? Can the thermal performance of CMOS 2.0 platforms be controlled? Only time will tell. To quote the German philosopher and revolutionary Friedrich Engels: “No one knows exactly the revolution he is creating.” At the same time, that’s what makes these times so fascinating. Exploring these uncharted territories requires close collaboration and co-innovation across the semiconductor ecosystem. What is threatened is not Moore's Law itself, but the ability it represents to promote economic growth, scientific progress and sustainable innovation.

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