Several issues about dual-port RAM memory

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Several issues about dual-port RAM memory [Copy link]

Dual-port RAM is a common shared multi-port memory. Its biggest feature is shared storage data, that is, one memory is equipped with two sets of independent address lines, data lines and control lines, allowing two independent CPUs or controllers to access the storage unit asynchronously at the same time. This simultaneous asynchronous access to the storage unit requires the control of the internal arbitration control logic (BUSY function output). Since the two ports have the following four situations when accessing the dual-port RAM:
1. The two ports do not access data to the same address unit at the same time;
2. The two ports read data from the same address unit at the same time;
3. The two ports write data to the same address unit at the same time;
4. The two ports operate on the same address unit at the same time, one writes data and the other reads data.
Therefore, the internal arbitration control logic provides the following functions accordingly:
1. Timing control of access to the same address unit;
2. Access rights allocation of storage unit data blocks;
3. Signaling exchange logic.

Timing control of access to the same address unit

When the left and right ports do not access the same address unit, BUSY R=H, BUSY L=H, and storage is allowed normally; when the left and right ports store data in the same address unit, BUSY=L of one port prohibits data access. At this time, BUSY=H corresponding to the storage request signal that appears first in the two ports, and storage is allowed. BUSY=L corresponding to the storage request signal that appears later, and storage is prohibited (Note: the time difference between the storage request signals of the two ports should meet the arbitration minimum time interval TAPS (5ns for IDT7132), otherwise the arbitration logic cannot determine which port's storage request signal comes first); when it is impossible to determine which port has the storage request signal first, only one of the control lines BUSY L and BUSY R is low, and they will not be low at the same time, thus avoiding errors in dual-port access.

Assigning access rights to storage unit data blocks

The access rights allocation of the data block of the storage unit only allows one CPU to perform read and write operations on a certain data block within a certain period of time, which will help protect the stored data and more effectively avoid address conflicts. Semaphore (SEM) arbitration lock is a method of implementing access rights allocation by combining hardware circuits with software. The SEM unit is a *** flag unit that is independent of the storage unit. Two ports use two triggers to achieve this function. When initialized, both triggers make the SEM allow output high and wait for both parties to apply for SEM. If a SEM signal written by one party is received (usually written at a low level), the arbitration circuit will make the SEM allow output of one of the triggers low and lock the other SEM allow output to keep it high. Only when the party that requested first cancels the SEM signal, that is, writes a high level, can the lock of the other SEM allow output be released and resume waiting for new SEM applications.

Signaling logic

In order to improve the data exchange capability, some dual-port RAMs use signaling exchange logic to notify each other, which is similar to the mailbox mechanism that synchronizes the process of the PC operating system.

The above is the arbitration logic control provided by the dual-port RAM itself. You can also use a self-designed arbitration protocol, such as FIFO.