Domestic computational lithography delivers good news again

Latest update time：2024-01-09

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/Introduction/

In the modern chip manufacturing process, photolithography is a very important step. The process uses a camera-like principle. The light emitted by the photolithography machine is exposed and imaged on the wafer through a patterned mask, thereby realizing the transfer of the circuit diagram. onto the wafer. Ideally, the image pattern on the wafer will be exactly the same as the layout design on the mask. However, when the critical dimension of the mask pattern is smaller than the exposure wavelength, the image on the wafer will be distorted due to the diffraction effect, which does not match the layout pattern of the mask. At this time, it is necessary to calculate the photolithography OPC (Optical Proximity Correction) Technology corrects the pattern of the mask to ensure that the pattern printed on the wafer conforms to the original design.

Dongfang Jingyuan has focused on the field of computational lithography since its establishment and launched the PanGen platform. After nearly ten years of development, PanGen has become a platform that integrates accurate process simulation, DRC, SBAR, OPC, LRC, DPT and SMO and other complete functional chains. At the same time, through rich and large-scale production line applications, Dongfang Jingyuan has become a pioneer and leader in the field of domestic computational lithography. Recently, based on industrial applications and development pain points, Dongfang Jingyuan launched two new products, PanGen DMC and PanGen dFO. This article will introduce in detail the research and development background, applications and results of these two products.

PanGen DMC——

Provides more comprehensive manufacturability checks based on rapid process feedback

As technology nodes evolve, the process itself becomes more and more complex, and it becomes increasingly difficult for designers to have a comprehensive and systematic understanding of the process. As a result, new products require repeated iterations and longer yield ramping during tape-out at the process end. It increases the cost of chip production and also extends the time for products to be launched. According to McKinsey statistics, it currently takes about 12 to 18 months for new products in the semiconductor industry to undergo repeated iterations from tape-out to final yield (Yield) ramp-up. If the Designer can obtain more and more comprehensive process information in advance, this will The process can be greatly simplified and accelerated, thereby improving yield and reducing costs.

(Picture from McKinsey official website)

Based on the solid computational lithography platform PanGen and rich industrial practical experience, Dongfang Jingyuan innovatively developed the PanGen DMC (Design Manufacturability Check) product, which has a built-in D2C (Design To Contour) fast lithography feedback engine, which can integrate the full set of FAB The OPC Recipe solution is packaged in the form of an AI model, allowing users to quickly and accurately estimate the topography (Contour) of the Design on the final silicon wafer based on the original Design, thereby predicting potential risks in the design layout in advance.

The D2C engine can accurately capture the behavior of the entire OPC Recipe and give Contour results that are very close to the complete OPC Recipe. It can be seen intuitively from the figure below that for the Metal and Via process layers (Layer) with different geometric characteristics, the Contour given by D2C and the Contour given by the complete OPC Recipe are almost consistent, even if multiple processes are comprehensively calculated The results of PV Band (Peak and Valley Band) under the conditions are also very close.

Taking a complete 28nm node RISC-V full chip layout as an example, the difference between the Contour given by D2C and the Contour given by the complete OPC Recipe under different process conditions (PW conditions) is basically less than 1nm, and the computing speed is much faster. Higher than the complete OPC Recipe, the current version can be measured to be about 80 times faster.

As process technology becomes increasingly complex, it is difficult to include all aspects of the entire process by relying solely on abstract rules. Therefore, if a design layout passes the rule-based DRC (Design Rule Check) check, it does not mean that it can have good performance on the process side. Performance. PanGen DMC can predict the final lithography topography of the design layout and provide process-side feedback in a more comprehensive and intuitive way. In addition, the DRC inspection only tells a black-and-white conclusion about whether a violation is violated. It is impossible to know how much impact a certain degree of violation will have on the process. Based on the model, PanGen DMC can present the impact to users in a very visual way, helping users to weigh violation handling according to the situation in practice. Therefore, this product can be a very powerful supplement to the existing DRC (Design Rule Check) tool for both the manufacturing and design ends. On the basis of respecting the customer's existing workflow, it can help customers make more comprehensive discoveries beyond DRC inspection. The risk of layout in terms of process manufacturability can be accelerated to accelerate iteration and reduce time costs, so that new chip products can increase the yield faster during the tape-out process and be launched to the market earlier.

PanGen dFO——

Effectively eliminate dead pixels and provide a more thorough OPC solution

When the wafer factory performs OPC, it will develop OPC Recipe based on the characteristics of each process layer layout of the specific technology node, such as the OPC Recipe for the metal layer of the 28nm technology node. OPC Recipe is essentially a series of optimization strategies and parameter settings that can convert the input original layout of the entire process layer into a mask pattern that can be imaged on the silicon wafer according to the desired shape. When developing OPC Recipe, we will consider the diverse graphics inputs under this technology node, and perform OPC optimization on the design layout before conducting photolithography simulation inspection (LRC). If the inspection finds that there are bad pixels, the OPC Recipe will be iteratively improved, thereby Make OPC Recipe fully responsive to various design layouts as much as possible. Once the OPC Recipe is determined, it will be transferred from the R&D department of the wafer factory to the mass production department and put into mass production.

However, no gold is pure and no tool is perfect. In practice, OPC Recipe may not be able to cover the patterns at certain positions of some layouts well, and its output mask pattern cannot give the expected imaging results, resulting in bad pixels (Hot Spot), affecting the final chip yield, which is an actual pain point that the wafer factory needs to face. At this time, it is necessary to make partial modifications to the mask pattern based on the feedback from the lithography simulation test (LRC), that is, Mask Repair.

Mask Repair can effectively help OPC engineers eliminate bad pixels, but it may modify the mask locally too much, resulting in extreme graphics shapes, which will be too sensitive to process disturbances in mask manufacturing, causing new problems; and in some cases, The shape of the design layout will naturally lead to poor imaging quality. At this time, repeated iterations of the Repair Mask will make it difficult to converge to a more ideal result!

Based on the existing computational lithography platform PanGen, Dongfang Jingyuan innovatively expanded local Mask Repair to local Design fine-tuning and launched the PanGen dFO (defect free OPC) product. With a progressive strategy, it continues to Automatic defect detection and leak filling can provide a more thorough OPC solution. In practice, for the dead pixels discovered by full-chip lithography simulation inspection (LRC), the local Mask Repair method is first used. If it can be directly solved, the processing of the dead pixels is completed. If it cannot be solved, the bad pixel will be solved through local automatic fine-tuning of the design. For example, if there are 1,000 bad pixels at the beginning, a considerable part of them may have been solved in the first step of local Mask Repair, and only a few remaining bad pixels will enter the next step of local fine-tuning design.

Based on the photolithography simulation feedback, the design layout is automatically fine-tuned locally. The changes to the entire design are minimal and have no impact on the function of the chip design itself. However, it can produce very positive help for the actual photolithography. It is a big deal and can be used for some stubborn people. Bad pixels can have the effect of clearing the air and revealing the sun. As shown in the figure below, 0.2 nm Design is automatically fine-tuned with remarkable results:

The following test example is based on a 4000um * 4500um complete RISC-V chip M2 layer at the 28nm node. It can be seen that through the continuous improvement of PanGen dFO, the number of dead pixels has been significantly reduced.

OPC plays an extremely critical strategic hub role in the semiconductor industry chain. Without OPC, fabs with all advanced nodes will lose the ability to convert chip designs into chip products, but the intractable bad pixels are like a few flowers on a sunny sky. Dark clouds restrict the more universal function of OPC Recipe, thereby affecting the production efficiency and yield of the wafer factory. PanGen dFO is based on Dongfang Jingyuan's existing technical elements and innovatively integrates partial Mask Repair and partial Design fine-tuning in a progressive manner. It continuously checks for deficiencies and resolves stubborn bad points that are difficult to solve in OPC Recipe. Wafer fabs can improve yield rates more efficiently and provide more help!

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