TSMC’s future depends on these technologies

With the development of AI, 5G and other advanced process technologies, the world is generating a large number of computing workloads through smart edge networks, requiring faster and more energy-efficient chips to meet this demand.

It is estimated that by 2030, due to surge in demand, the global semiconductor market will be approximately US$1 trillion, of which high-performance computing (HPC)-related applications will account for 40%, smartphones will account for 30%, automobiles will account for 15%, and the Internet of Things will account for 10%. - TSMC and its partners created more than 12,000 innovative products in 2022, using nearly 300 different TSMC technologies.

TSMC continues to invest in technologies such as advanced logic processes, 3DFabric, and special processes to provide the right technology at the right time to help drive customer innovation. As our advanced process technology advances from 10 nanometers to 2 nanometers, our energy efficiency increases at a compound annual growth rate of 15% in approximately ten years to support the incredible growth of the semiconductor industry.

The compound annual growth rate of TSMC's advanced process technology production capacity will exceed 40% from 2019 to 2023. As the first fab to start mass production of N5 in 2020, TSMC continues to strengthen its 5nm family by launching technologies such as N4, N4P, N4X and N5A. TSMC’s 3nm process technology is the first in the semiconductor industry to achieve high volume production and high yield. We expect N3 to achieve rapid and smooth ramping driven by mobile and HPC applications.

In addition, in order to further promote scaling and realize smaller and better transistors in monolithic SoCs, TSMC is also developing 3DFabric technology to take advantage of heterogeneous integration and integrate the transistors in the system. Increase the quantity by 5 times or more.

From 2017 to 2022, TSMC’s investment in special process technology will have a compound annual growth rate of more than 40%. By 2026, TSMC expects to increase its special process production capacity by nearly 50%

N2 is planned for mass production in 2025; N2P and N2X are planned to be launched in 2026.

The performance of nanosheet transistors has exceeded 80% of TSMC's technical goals, while demonstrating excellent energy efficiency and lower operating voltage (Vmin), making it very suitable as a model for energy-saving computing in the semiconductor industry. As part of TSMC's N2 process technology platform, the backside power rail design provides additional speed and density improvements to its baseline technology. The rear power rail design is best suited for HPC products and will be launched in the second half of 2025. By reducing voltage drop (IR drop) and signal resistor-capacitor delays (signal RC delays), the speed is increased by more than 10-12%. Since the front side of the wafer has more wiring resources, the logic area can be reduced by 10-15%.

N3 is TSMC's most advanced logic process technology and has entered mass production in the fourth quarter of 2022 as planned; N3E is planned to be launched one year after N3 mass production and has passed technical verification and achieved performance and yield targets. Compared with N5, N3E is 18% faster at the same power consumption, 32% lower at the same speed, has a logic density increase of approximately 60%, and a chip density increase of approximately 30%. o N3E has received the first batch of customer product design finals (product tape-outs) and will begin mass production in the second half of 2023.

TSMC has also launched N3P and N3X to enhance the value of process technology. While providing additional performance and area advantages, it also maintains design rule compatibility with N3E to maximize IP reuse. In the first three years of mass production, the number of new product designs finalized for N3 and N3E will be 1.5 to 2 times that of N5 during the same period, mainly due to TSMC's technological differentiation and readiness.

While maintaining compatibility with N3E design rules, it provides additional performance and area advantages to maximize IP reuse. N3P is expected to start mass production in the second half of 2024. Customers can achieve a 5% faster speed under the same leakage power, a 5-10% reduction in power consumption at the same speed, and a 4% increase in chip density compared to N3E. o N3X: Specifically designed for HPC applications, it provides an additional maximum oscillation frequency (Fmax) to improve overdrive performance under moderate leakage balance. This means that compared to N3P, N3X operates at a driving voltage of 1.2 volts. , the speed is increased by 5%, and has the same chip density increase. N3X is expected to enter mass production in 2025.

TSMC today launched the industry's first 3nm-based Auto Early technology, named N3AE. N3AE provides an automotive process design kit (PDK) based on N3E, allowing customers to adopt 3 nanometer technology to design automotive application products early, so that they can adopt the N3A process in time in 2025, which has been fully verified by the automotive process.

As TSMC's 5-nanometer process enters mass production, the accumulated experience has enabled the process's yield and efficiency to continue to improve. In 4 years, compared with the first year of N5 mass production, TSMC has improved the performance of the process by up to 17%, increased the chip density by 6%, and maintained the same design rule compatibility to maximize the number of existing customers. Design reuse. Although N5 demand is strong, N4P will drive demand to increase further from 2024. Compared with 2022, this increase in demand mainly comes from artificial intelligence, network and automotive products, which is closely related to industry trends.

Transistor architecture has evolved from planar to FinFET and is about to transition to nanosheet architecture. After nanosheets, TSMC believes that vertically stacked NMOS and PMOS (complementary field effect transistor CFET) are one of the future process architecture options.

TSMC estimates that after taking into account wiring and process complexity, chip density will be increased by 1.5 to 2 times. In addition to CFET, TSMC has made breakthroughs in low-dimensional materials (such as carbon nanotubes and 2D materials), which may enable further size and energy shrinkage.

TSMC's 3DFabric system integration technology includes a variety of advanced 3D silicon stacks and advanced packaging technologies to support a wide range of next-generation products:

In terms of 3D silicon stacking, TSMC is adding micro-bumped SoIC-P to the system integrated chip (TSMC-SoIC®) family to support more cost-sensitive applications. The 2.5D CoWoS platform enables the integration of advanced logic and high-bandwidth memory, suitable for HPC applications such as artificial intelligence, machine learning, and data centers; integrated fan-out package-on-package technology (InFO PoP) and InFO-3D support mobile applications, InFO-2.5 D supports HPC chiplet integration. System-on-chip (SoIC) stack chips can be integrated into integrated fan-out (InFO) or CoWoS packages for ultimate system integration.

The CoWoS family is mainly targeted at HPC applications that require the integration of advanced logic and high-bandwidth memory. TSMC already supports more than 140 CoWoS products from more than 25 customers. The interposer area of ​​all CoWoS solutions is increasing to integrate more advanced silicon and high-bandwidth memory stacks to meet higher performance demands. TSMC is developing CoWoS solutions with up to six mask-sized (approximately 5,000 square millimeters) redistribution layer (RDL) interposers capable of accommodating 12 high-bandwidth memory stacks.

Coming to InFO process technology, in terms of mobile applications, InFO PoP has been mass-produced and used in high-end mobile devices since 2016, and can accommodate larger and thicker system-on-chip (SoC) in smaller package specifications. In terms of HPC applications, the substrate-less InFO_M supports the integration of small chips up to 500 square millimeters and is suitable for applications that are highly sensitive to form factors.

As for 3D silicon stacking technology, SoIC-P uses 18-25 micron pitch micro-bump stacking technology, mainly targeting more cost-sensitive applications such as mobile, Internet of Things, and customer applications. SoIC-X uses bump-less stacking technology and is mainly targeted at HPC applications. Its chip-to-wafer stacking solution has a bonding pitch of 4.5 to 9 microns and has been mass-produced in TSMC's N7 process technology for HPC applications. SoIC stack chips can be further integrated into CoWoS, InFo or traditional flip-chip packages for use in customers' final products.

AMD successfully demonstrated the use of SoIC-X technology to stack N5 GPU and CPU on the underlying chip and integrate them in the CoWoS package to meet the needs of next-generation exa-scale computing. This is TSMC's 3DFabric Concrete examples of how technology is driving innovation in HPC.

TSMC provides the industry's most comprehensive portfolio of special process products, including power management, radio frequency, CMOS image sensing, etc., covering a wide range of application fields.

Let’s look at automobiles first. As the automobile industry develops towards autonomous driving, computing requirements are increasing rapidly and the most advanced logic technology is required. By 2030, TSMC expects that 90% of cars will be equipped with advanced driver assistance systems (ADAS), of which L1, L2 and L2+/L3 are expected to each reach a market share of 30%.

Over the past three years, TSMC has launched the Automotive Design Implementation Platform (ADEP) to unleash customers' automotive innovation by delivering industry-leading, Grade 1 quality-certified N7A and N5A. In order to allow customers to design automotive products in advance before the technology matures, TSMC launched Auto Early as a stepping stone to start product design early and shorten the time to market. N4AE is a new technology developed based on N4P that will allow customers to start risk production in 2024. N3AE serves as the solid foundation of N3A. N3A will fully pass automotive process verification in 2025 and will become the world's most advanced automotive logic process technology.

In response to the advanced radio frequency technology needs of 5G and connectivity, TSMC launched N6RF in 2021. This technology is based on our record-breaking 7nm logic process technology and has best-in-class transistors in terms of speed and energy efficiency. efficacy. Combining outstanding RF performance with superior 7nm logic speed and energy efficiency, TSMC customers can achieve a 49% reduction in power consumption on half-digital and half-analog RF SoCs by switching from 16FFC to N6RF, unleashing mobility Device energy budget to support other growing functions.

TSMC recently announced the launch of the most advanced complementary metal oxide semiconductor (CMOS) radio frequency technology N4PRF, which is expected to be released in the second half of 2023. Compared with N6RF, N4PRF has a 77% increase in logic density and a 45% reduction in power consumption at the same performance. N4PRF also has a 32% increase in MOM capacitance density compared to its predecessor technology, N6RF.

TSMC also has ultra-low power solutions. According to reports, TSMC’s ultra-low power solutions continue to promote the reduction of Vdd to achieve energy savings that are crucial for electronic products. TSMC continues to improve its technology. From the minimum Vdd of 55ULP to 0.9 volts to the Vdd of N6e below 0.4 volts, we provide a wide voltage operating range to achieve dynamic voltage adjustment design to achieve the best power/performance. Compared with the N22 solution, the upcoming N6e solution can provide approximately 4.9 times the logic density and reduce power consumption by more than 70%, providing an attractive solution for wearable devices.

In terms of MCU/embedded non-volatile memory, TSMC's most advanced eNVM technology has been developed to based on 16/12nm fin field effect transistor (FinFET) technology, allowing customers to benefit from the excellent performance of FinFET transistors. As traditional floating gate eNVM or ESF3 technology becomes more and more complex, TSMC has also invested heavily in new embedded memory technologies such as RRAM and MRAM. Both new technologies have already yielded results and are in production at 22nm and 40nm. TSMC is planning to develop 6nm technology.

Coming to RRAM, TSMC has started producing 40/28/22nm RRAM in the first quarter of 2022. TSMC's 28nm RRAM is progressing smoothly, with reliable performance and suitable for automotive applications. TSMC is developing the next generation of 12nm RRAM, which is expected to be ready in the first quarter of 2024.

The 22nm MRAM that Taichi has also started producing in 2020 is mainly used for Internet of Things applications. Now, TSMC is working with customers to apply MRAM technology to future automotive applications and is expected to achieve Grade 1 in the second quarter of 2023. Automotive grade certification.

As for CMOS image sensing, while smartphone camera modules have been the main driver of complementary metal oxide semiconductor (CMOS) image sensing technology, TSMC expects automotive cameras to drive the next wave of CMOS image sensors (CIS) grows. In order to meet the needs of future sensors and achieve higher quality and smarter sensing, TSMC has been working on multi-wafer stack solutions to demonstrate new sensor architectures, such as stacked pixel sensors and smallest-volume global shutters. sensors, event-based RGB fusion sensors, and AI sensors with integrated memory.

For display applications, driven by technologies such as 5G, artificial intelligence, and AR/VR, TSMC is committed to providing higher resolution and lower power consumption for many new applications. The next generation of high-end OLED panels will require more digital logic and static random access memory (SRAM) content, as well as faster frame rates. To meet such needs, TSMC is introducing its high-voltage (HV) technology to 28nm product generation to achieve better energy efficiency and higher SRAM density. TSMC's leading µDisplay on silicon technology can deliver up to 10x the pixel density to achieve the higher resolution required for near-eye displays such as those used in AR and VR.

In order to meet the growing needs of customers, TSMC has accelerated the pace of wafer fab expansion. From 2017 to 2019, TSMC conducted an average of approximately two phases of wafer fab construction projects each year. From 2020 to 2023, the average construction progress of TSMC's wafer fabs has increased significantly to about 5 phases of projects per year.

In the past two years, TSMC has launched a total of 10 phases of new wafer fab construction projects, including the 5th phase wafer fab project and the 2nd phase advanced packaging plant project in Taiwan, as well as the 3rd phase wafer fab project overseas.

Overseas production capacity for 28nm and below processes will triple in 2024 compared to 2020.

In Taiwan, TSMC's N3 process mass production base is at Nanke 18 Factory; in addition, TSMC is preparing for a new wafer fab for the N2 process. In the United States, TSMC is building a Phase 2 fab in Arizona.

The company's first phase N4 wafer fab has begun moving in equipment and will start production in 2024. The second phase of the wafer fab is under construction and is planned to be produced using the N3 process. The two phases of the fab will have a combined annual output of 600,000 wafers.

In Japan, TSMC is building a wafer fab in Kumamoto and plans to provide wafer manufacturing services in the 16/12nm and 28nm families to respond to the strong demand for special processes in the global market. Construction of this wafer fab has begun and will enter mass production in 2024.

In China, the new phase 1 28nm process wafer fab will begin mass production in 2022.

TSMC’s leadership in defect density (D0) and defects per million (DPPM) for advanced processes demonstrates its manufacturing excellence.

The process complexity of N5 is much higher than that of N7, but at the same stage, the yield optimization of N5 is better than that of N7.

TSMC's N3 process technology leads the industry in yield performance in high-volume production, and its D0 performance is already comparable to N5's performance over the same period.

TSMC's N7 and N5 process technologies have demonstrated industry-leading DPPM in smartphones, computers, and automobiles. We believe that N3's DPPM will soon catch up with N5's performance.

By leveraging TSMC's industry-leading 3DFabric manufacturing technology, customers can overcome the challenges of system-level design complexity and accelerate product innovation. The CoWoS and InFO families achieved very high yields very quickly after mass production. The integrated yield of SoIC and advanced packaging will reach the same level as CoWoS and InFO families.

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