Intel says it is regaining its leadership in chip manufacturing

The next wave of Moore's Law will rely on a development concept called co-optimization of system technologies, Ann B. Kelleher, Intel's general manager of technology development, told IEEE Spectrum in an interview ahead of her plenary address at the 2022 IEEE Electronic Devices Conference.

"Moore's Law is about increasing the integration of functionality," Kelleher said. "Looking forward to the next 10 to 20 years, there will be a path full of innovation," and the rhythm of improving products every two years will continue. This path includes continuous improvements to semiconductor processes and designs in general, but System Technology Co-Optimization (STCO) will make the biggest difference.

Kelleher calls it an "outside-in" approach to development. It starts with the workloads the product needs to support and its software, then drills down to the system architecture, then what type of silicon must be used in the package, and finally to the semiconductor manufacturing process. “Co-optimization with system technology means all the parts are optimized together so you get the best answer for the final product,” she said.

STCO is now an option largely because advanced packaging such as 3D integration allows high-bandwidth connectivity of chiplets (small functional chips) within a single package. This means that functions that were once on a single chip can be broken down into dedicated chiplets, each of which can then be manufactured using optimized semiconductor process technologies. For example, Kelleher noted during her plenary session that high-performance computing requires large amounts of cache per processor core, but chipmakers' ability to shrink SRAM has not kept pace with logic shrink. Therefore, it makes sense to build the SRAM cache and compute cores as separate chiplets using different process technologies, and then stitch them together using 3D integration.

Kelleher said a key example of STCO is the Ponte Vecchio processor at the heart of the Aurora supercomputer. It consists of 47 active chiplets (and 8 blanks for heat transfer). They are stitched together using advanced horizontal joining (2.5 packaging technology) and 3D stacking. “It brings together silicon from different fabs and enables them to be combined so that the system can perform for the workload it was designed for,” she said.

Intel sees a concept called system technology co-optimization as the next phase of Moore's Law.

At IEDM, Intel engineers will report that their 3D hybrid bonding technology offers a tenfold improvement in density over what was reported in 2021. Increased connection density means more chip functionality can be broken out onto separate chiplets, providing more potential to use STCO to improve outcomes. With this new technology, the hybrid bond pitch (ie, the distance between interconnects) is only 3 microns. This way, more cache can be decoupled from the processor core. According to Kelleher, reducing the bond pitch to between 2 microns and 100 nanometers could mean being able to start separating logic functions that today must be on the same piece of silicon.

The drive to optimize systems by breaking down functionality is having an impact on future semiconductor manufacturing processes. Future semiconductor process technologies must cope with the thermal stress of the 3D packaging environment. But interconnect technology may see the biggest changes. Kelleher said Intel is expected to launch a technology called PowerVia (more generally, backside power supply) in 2024. PowerVia moves the chip's power supply network beneath the silicon, reducing the size of the logic cells and reducing power consumption. But it also "gives us different opportunities in terms of what we can do and how we interconnect in the package," Kelleher said.

System Technology Co-Optimization (STCO) optimizes more parts of a computer system by considering all aspects from software to process technology.

Kelleher emphasized that STCO is still in its infancy. Electronic design automation (EDA) tools have addressed STCO's predecessor, design technology co-optimization (DTCO), which focused on logic cell-level and functional block-level optimization. "But some EDA tool vendors are already working on solving this problem," she said. “Going forward, the focus will be on methods and tools that help achieve STCO.”

As the STCO evolves, equipment engineers may have to evolve with it. “In general, engineers need to continue to develop knowledge of their equipment, but also start to understand the use cases for their technology and equipment,” Kelleher said. “As we move into more of the STCO world, more interdisciplinary skills will be needed.”

Kelleher also updated Intel's roadmap, tying it to advances in Moore's Law and the evolution of devices since the invention of the first transistor. Kelleher said things have been on track since Intel announced its new manufacturing roadmap less than two years ago. But she did fill in some details about the processors that will debut alongside the new technology.

Intel is on track to develop its process technology roadmap.

The Intel 20A is scheduled to enter production in the first half of 2024 and is still a major leap in technology. It also introduces a new transistor architecture - RibbonFET (commonly known as gate-all-around or nanosheet transistor) and PowerVia backside power delivery. When asked about the risks involved, Kelleher explained the strategy.

"They don't have to do it immediately, but we see significant benefits in moving to PowerVia to enable [RibbonFET] technology," she said. Development is being done in parallel to reduce the risk of delays, she explained. Intel is running the test process using FinFET (the transistor architecture used today) and PowerVia. “This has been very successful and it has allowed us to accelerate our development efforts,” she said.

Kelleher's speech comes as the IEEE Electronic Devices Society celebrates the 75th anniversary of the invention of the transistor. At IEEE Spectrum, we asked experts what transistors will look like on their 100th birthday in 2047. Kelleher considered the long life of transistor technology, noting that planar transistor designs lasted from 1960 to about 2010, and that its successor, FinFET, is still going strong. "Now we're going to move to RibbonFETs, which will probably last another 20-plus years...so I expect we'll have stacked RibbonFETs," she suggested. [Intel engineers describe the technology in the December 2022 issue of IEEE Spectrum.] By then, however, the ribbons may be made of 2D semiconductors rather than silicon.

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