In the post-NAND era, this will become the storage option of the future

Latest update time：2022-05-17

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Today's memory landscape includes different types of memory, each of which plays a role in storing data and feeding it back to the computing portion of an electronic system. In the traditional computer hierarchy, fast and more expensive active memories - static random access memory (SRAM) and dynamic RAM (DRAM) - are differentiated from higher latency and lower cost storage solutions.

Storing large amounts of data is primarily done with NAND Flash, hard disk drives (HDDs), and tape technologies. While tape storage is still limited to long-term archiving, HDDs and NAND-Flash are used for online and near-line storage applications: they both require more frequent access than tapes, with access times ranging from microseconds to seconds. NAND-Flash offers the lowest latency and power consumption of the two storage types. This non-volatile memory is found in all major electronic end markets, such as smartphones, servers, PCs, tablets, and USB drives.

Figure 1. Schematic overview of today’s major memory technologies and their application areas, illustrating the trade-off between latency and productivity.

Over the years, researchers have been able to significantly increase the bit density of various storage solutions to keep up with the growing demand. However, for several years, HDD technology has failed to follow the historical productivity trend line. A similar time delay is expected for NAND-Flash technology.

^{3D-NAND-Flash is expected to reach storage densities of up to 70Gbit/ mm2} by 2029 , which will slow down by about four years relative to the historical density expansion roadmap.

Entering the post-NAND era

After NAND-Flash scaling saturates, we expect different storage technologies to coexist, each with tradeoffs in size, power consumption, latency, and cost. New concepts in storage are being investigated, not to replace existing storage solutions, but to complement them in the latency/productivity space.

Think of DNA storage for low-cost, ultra-high-density but slower archival applications (e.g. preserving (surveillance) video, medical and scientific data) or ferroelectric storage technologies expected to find their place in the low-latency storage market segment. All of these memories will be organized in different tiers and will collectively address the storage needs of the >100 zettabyte data era.

In this paper, we propose two new liquid-based storage concepts: colloidal

) and electrolithic memory – have the potential for ultra-high-density nearline storage applications. For example, these storage solutions can make archived “inactive” data (such as email archives, image and sound files or other large documents) accessible to users within seconds. From 2030 onwards, they may find their place between HDD and tape, with much higher bits per reel, but slower than 3D-NAND-Flash.

Increasing bit density requires new ways to address memory cells

We believe that there is a fundamental reason why it is challenging to further expand the bit density of traditional solid-state memories such as SRAM, DRAM or 3D-NAND-Flash in a cost-effective way. In all these memories, the memory cells are organized in a two-dimensional or three-dimensional array, located at the intersection of word lines and bit lines. Each cell consists of at least one storage element and one access device. The access device - usually a transistor or a diode - connects the storage element to at least two lines for selecting, reading and writing the memory cell.

The scaling challenge has nothing to do with the memory element itself (memory elements the size of a single molecule have been demonstrated) but rather with the access device and its wiring.

The size of the cell is at least 2Fx2F (4F ² ), where F is the minimum feature size (e.g., wordline half pitch), determined by the (expensive) photolithography steps used to pattern the wires. This configuration of one access device per storage element makes it challenging to develop cost-effective high-density solutions and store more than a few bits per cell (currently a maximum of 4 bits for NAND-Flash cells).

HDD and tape storage technologies use a different strategy. Here, a significantly smaller number of read/write access devices are connected to a larger unpatterned area that serves as the storage medium. This results in higher densities and lower cost per bit compared to NAND Flash. But it also makes for a slower, more bulky and energy-consuming solution - because the read head must be mechanically positioned over a large area.

Disruptive solution couples dense arrays of access devices to capacity storage media

By reconciling the best of both worlds, new ways could be found to create ultra-high-density storage devices that have an affordable cost per bit and operate faster than magnetic tape.

An attractive approach to enable ultra-high density storage devices is to make dense arrays of access devices connected to a storage medium. Inspired by advances in life sciences, this storage medium could be a liquid containing ions, molecules or (nano)particles that can be manipulated and moved in larger volumes to access devices that are part of a dense array.

This approach would enable multi-bit operations with significantly fewer access devices, wires, and lithography steps required for each bit. The high-density potential of this new approach has attracted interest from industry, and several liquid-based concepts are being investigated worldwide.

Figure 2. Three different types of addressing used in memory technology

Below, we present two new liquid-based concepts with long-term near-line storage potential, targeting (sub) second access times. In this paper, the focus is on their working principles and first experimental results. More details were presented at IMW 2022, and the work on carbide memory was recently published in IEEE Transactions on Electron Devices.

Colloidal memory: Manipulating nanoparticles

The first liquid-based memory concept introduced by imec is called colloidal memory.

The colloidal memory concept nicely demonstrates how liquids (e.g., water) can be used as a volume storage medium and dissolved nanoparticles (colloids) as carriers of data symbols.

The idea is to use a colloid of (at least) two types of nanoparticles (A and B) that are contained in a reservoir. This reservoir is connected to an array of capillaries, into which the nanoparticles can be inserted. If the nanoparticles are only slightly smaller than the diameter of the capillaries, the order in which the particles (bits) entered the capillaries can be preserved. It is in this sequence of bits that the information can be encoded. The nanoparticles can be selectively induced (and sensed) by electrodes located at the entrance of each capillaries. A CMOS peripheral circuit controls the electrode array.

Figure 3. Schematic diagram of the colloidal memory concept

One of the main challenges concerns the sequence of "writing" the nanoparticles, in other words, the selective attraction and insertion of the particles into the capillaries. Imec researchers are exploring theoretically and experimentally the feasibility of using frequency-dependent dielectrophoresis as a writing mechanism. According to this mechanism, an alternating electric field generated across electrodes exerts a force on the nanoparticles. Whether this force is attractive or repulsive depends, among other things, on the type of particle and the frequency of the induced electric field. A selective writing process can be created by choosing two particles that respond differently to the applied frequency (attraction vs. repulsion).

Colloidal memory technology is in the exploratory phase of research and development. The first set of experiments with µm-sized electrodes in different configurations, including interdigital and checkboard arranged arrays, marked the first milestone. Using the dielectrophoresis effect, they demonstrated the feasibility of selectively extracting polystyrene nanoparticles from a mixed solution. But the required technology still requires significant development. Further studies are ongoing to fine-tune the concept and provide a first proof of principle at the nanoscale.

Figure 4. Demonstration of the writing process: (fluorescent) polystyrene nanoparticles are attracted by the alternating electric field generated by electrodes arranged in a checkerboard pattern.

Calcium carbide storage: using electrochemistry

Like colloidal memory, carbide memory uses a fluid reservoir and array of capillaries, but in this case the metal ions are dissolved in a liquid and read and write operations are performed using more conventional electrodeposition and dissolution techniques.

In more detail, the reservoir contains a fluid in which (at least) two metal ions (A and B) are dissolved. The reservoir is connected to a series of capillaries (or wells). A working electrode (made of an inert metal such as ruthenium (Ru)) is located at the bottom of each capillary. The reservoir is also in contact with a single counter electrode. The reservoir, working electrode and common counter electrode together form an electrochemical cell for each capillaries . The dense array of working electrodes is connected to a CMOS integrated circuit for individually addressing each electrode.

By applying a certain potential to the working electrode inside the capillaries , a thin layer of metal A can be deposited on the electrode. Metal B behaves similarly, but the deposition starts at a different potential - determined by its chemical nature.

Information could now be encoded in stacks of alternating layers, suggestive of a lithos—hence the name of the new memory.

Figure 5. Schematic diagram of calcium carbide storage concept

We can now think of several ways to encode information. In one possible encoding scheme, 1nm of metal A can be used to encode binary 0, while a 2nm thick layer of A encodes binary 1. A layer of metal B of fixed thickness (e.g., 0.5nm) can be used to delineate subsequent layers. In fact, assuming that the starting potential of B is higher than that of A, the metal B layer will alloy with a certain amount of A. The carbide memory can be read by reversing the cell current and monitoring the dissolution potential.

In a first proof of concept using millimeter- and micrometer-sized electrodes, the feasibility of reading and writing using these technologies could be successfully demonstrated. For example, for electrodes with a diameter of 4µm, the researchers demonstrated continuous writing and reading of two layers of CoNi alternating with three layers of Cu. The experiments also showed that micrometer-sized electrodes have shorter write/read times than larger electrodes.

Figure 6. Top view SEM showing a microelectrode array with electrodes of varying sizes ranging from millimeters to micrometers: a first proof of concept

Ultimately, tightly spaced nanoscale wells are needed to achieve sufficiently high bit densities and response times. Therefore, imec researchers have fabricated second-generation carbide memory cells designed to write and read signals from extensive arrays of parallel nanowells (80-150 nm in diameter and 300 nm deep). Preliminary results show that the read signal obtained after dissolving the Cu/CoNi five-layer stack corresponds well to the write (i.e. deposition) operation (see Figure 7).

Figure 7. (Left) Second-generation calcium carbide memory cell with nanopores and common bottom electrode; (Middle) Schematic diagram of writing to a Cu/CoNi 5-layer stack, showing three different writing schemes; (Right) Read signal, clearly showing the position of the CoNi layer in the stack. For example, the first peak corresponds to the most recently deposited CoNi layer.

Towards industrial applications: Improving density, response time, bandwidth, endurance, and retention

These new liquid-based memories are still at the exploratory research stage, with calcium carbide memories being the most advanced. However, industry has shown considerable interest in these concepts.

At imec, we envision the introduction of liquid memory in the memory roadmap starting from 2030, when the bit density scaling of 3D-NAND-Flash will start to saturate.

With further scaling efforts, we expect that through these approaches, bit storage density can be pushed into the 1Tbit/mm2 ^{range
, with lower process costs per}^mm2 compared to 3D-NAND-Flash . For liquid memory, such high density can only be achieved with a spacing of 40nm between electrodes and capillaries. In addition, researchers must be able to manufacture capillaries with aspect ratios of approximately 400:1 and 165:1 for colloidal and carbide memory, respectively. This is similar to the aspect ratio of memory holes required to manufacture future 3D-NAND-Flash products and is therefore considered a realistic goal.

To become a viable memory solution for nearline applications, the technology must also have adequate response time, bandwidth (e.g. 20Gb/s), cycling endurance (103 ^write /read cycles), energy consumption (several pJ written bits), and retention (more than 10 years). These assessments will be the subject of further studies, built on imec’s 300 mm liquid memory testbed featuring colloidal and electrolithic cells in different configurations.

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