Video demonstration: How should PCIe 5.0 design be done?

Figure 1: Doubling of I/O bandwidth every three years and accompanying PCI specification updates

Nearly 20 years have passed since the advent of the PCIe standard. During this period, application diversity, bandwidth requirements, and hardware specifications have jointly promoted rapid growth in protocol rates.

Ethernet cards, solid-state storage, persistent memory, and FPGA-based accelerator cards all use this widely used interface. Following the trend of I/O bandwidth doubling every three years, PCI-SIG has been tracking the latest changes and adjusting the specifications to match accordingly.

In the United States, people use an average of 3 petabytes of data every minute. In the same minute, Google will receive 3.8 million queries (based on 2018 data, a full 2 ​​times the number in 2012!).

Our insatiable demand for computing power and data continues to drive increases in I/O bandwidth. In 2020, thanks to advanced technology, the sequencing of the SARS-CoV-2 novel coronavirus genome was completed in just a few weeks, and the clinical development of vaccines has also been greatly accelerated, which was almost a fantasy a few years ago.

We have officially entered the Zettabyte era. If the public's demand for video streaming media was the main reason for the surge in data flow in 2012, AI, machine learning and a series of intelligent applications have reshaped the distribution of computing power today, and with the development of process nodes, architecture, and protocols New opportunities are constantly being created.

Deep at the forefront of change, one of the challenges facing the computing industry is keeping power consumption low while meeting demand. The information industry has been criticized for not being environmentally friendly enough.

Servers and storage, as well as network equipment and data centers, usually run under conditions of low energy efficiency.

Figure 2: Cadence’s solution for PCIe 5.0 (PHY and controller subsystem SoC)

When a new version of the protocol is introduced to the market, PCI-SIG's official compliance program generally has not yet been launched.

In order to build enterprise and market confidence in the new standard, we need controller and PHY-based subsystems to demonstrate a complete PCIE protocol solution, and adopt this system to carry out protocol layer and electrical layer scope at a wide range of equipment vendors. test.

The Cadence PCIE subsystem SoC implements up to 8-lane link channels and has been tested at multiple equipment providers. Specific details will be shared with test partners in the video below.