Cadence digital and custom/analog design flows receive TSMC’s latest N2 process certification

Latest update time：2023-10-10

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Executive summary

Cadence digital workflow covers key new technologies, including a highly accurate and massively scalable parasitic 3D field solver

Cadence Cerebrus is driven by AI and supports the N2 process, which can significantly improve customer productivity

The customization/simulation process based on AI-driven Virtuoso Studio supports circuit optimization, and its functions have been enhanced to increase design migration throughput by 3 times.

Mutual customers of both parties are actively using N2 PDK to develop AI, large-scale computing and mobile ICs

Shanghai, China, October 10, 2023 - Cadence Electronics (Cadence, Inc., NASDAQ: CDNS) recently announced that its digital and custom/analog processes have passed Taiwan Semiconductor Manufacturing Co., Ltd.'s (TSMC) latest N2 Design Rule Manual (DRM) certification. Through this latest collaboration, the two companies will deliver a new N2 process design kit (PDK), allowing customers to easily and conveniently use the latest technologies from both companies, including Cadence ^® AI technology that helps improve design productivity. Mutual customers are already using N2 PDK to design innovative AI, large-scale computing and mobile applications to achieve design goals, simplify simulation migration and accelerate time to market.

Cadence digital process

The complete certified Cadence digital workflow includes the Innovus ^™ Implementation System, Quantus ^™ Extraction Solution and Quantus Field Solver, Tempus ^™ Timing Solution and ECO Option, Pegasus ^™ Verification System, Liberate ^™ Characterization Portfolio and Voltus ^™ IC Power Integrity Solution.

For more information about the digital process, please visit

www.cadence.com/go/cdnsdigitalff

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The digital full flow supports all the latest TSMC N2 PDK requirements, providing customers with several key new capabilities. In addition, Quantus Field Solver can model a large number of geometries and parasitic effects of N2 nodes, providing highly accurate models for SRAM, memory, and high-performance sensitive designs. The performance of the Innovus Implementation System engine has been improved again, using predictable and convergent processes to optimize utilization and achieve N2 design goals. Pegasus Verification System for physical signoff is tightly integrated with Cadence Virtuoso ^® Studio to effectively increase design productivity. Finally, Voltus IC Power Integrity Solution's voltage drop analysis across the front-end layer allows customers to build robust power networks to achieve voltage drop convergence.

Cadence Cerebrus ^™ Intelligent Chip Explorer also supports the N2 process, helping customers reduce the time spent on manual design processes and significantly increase productivity.

Cadence customization/simulation process

The Cadence customization/simulation process is TSMC N2 technology certified and is based on Virtuoso Studio, which includes Virtuoso Schematic Editor, Virtuoso ADE Suite and Virtuoso Layout Suite. Also included is the Specter ^® Simulation Platform, which includes products such as Specter X Simulator and Specter eXtensive Partitioning Simulator (XPS). The latest flow provides a complete suite of routing technologies covering all custom/analog topologies.

About Cadence customization/simulation process

For more information, please visit

www.cadence.com/go/cdnscustomanalog

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The new version of Virtuoso ADE architecture has been upgraded to allow users to run tens of thousands of simulation tests on modern computing clusters and public and private clouds. It can also reduce the memory footprint of Virtuoso. In addition, enhanced verification methods have been added to ensure that designs are robust and reliable. Specter FMC Analysis statistical technology quickly finds tail samples that may cause design failure. At the same time, users can also use new optimization algorithms to quickly adjust the migrated design according to the new specification tolerances.

Virtuoso Layout Suite has been upgraded to provide effective layout implementation on the TSMC N2 process, improving the performance of various functions, such as core editing commands, connection relationship extraction, layout browsing and exporting to abstract generation; the simulation unit has been enhanced through the orbit mode assistant joint; a unique non-uniform grid-based structured device placement method is added to assist users in interactively placing devices, wiring, filling and inserting; device-level automatic routing function is used to manage advanced Node complexity; automatic generation of guard rings based on DRM; integrated parasitic parameter extraction and EM-IR inspection; enhanced custom design migration and function reuse; seamless integration of place and route engine with Innovus Implementation System to improve quality of results (QoR).

"Thanks to our long-term partnership with Cadence, customers can use our latest N2 process technology and enhanced Cadence digital and custom/analog flows to build next-generation AI, hyperscale computing and mobile ICs," TSMC Design Infrastructure Management Business Dan Kochpatcharin, head of the department, said, "Cadence and TSMC work side by side with customers to gain a deep understanding of their most pressing design needs and fine-tune our solutions to better meet customer requirements and help them bring their products to market faster. Bring to market."

"Cadence continues to focus on innovation, and through this latest collaboration with TSMC, we are adding more new capabilities to the latest certified digital and custom/analog flows to help customers successfully develop N2 designs," said Cadence Senior Vice President, Digital "In addition, our AI-driven solutions Cadence Cerebrus and Virtuoso Studio provide customers with innovative automation capabilities that significantly improve design efficiency. We look forward to seeing our mutual customers Achieve design goals and launch high-quality design results to the market faster.”

Cadence digital and custom/analog design flows support Cadence's Intelligent System Design ^™ strategy to help customers achieve superior system-on-chip (SoC) design.

To learn more about Cadence Advanced Node

For solution information, please visit

www.cadence.com/go/advndn2pr

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About Cadence

Cadence is a key leader in electronic systems design with more than 30 years of expertise in computing software. Based on the company's intelligent system design strategy, Cadence is committed to providing software, hardware and IP products to help electronic design concepts become reality. Cadence's customers are the most innovative companies around the world, delivering chips and circuit boards to the most dynamic application markets such as hyperscale computing, 5G communications, automotive, mobile devices, aerospace, consumer electronics, industrial and medical. to complete systems of superior electronics. Cadence has been ranked among Fortune magazine's 100 Best Companies to Work For for nine consecutive years. For more information, please visit the company's website at www.cadence.com.

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