How can I improve my system clock or clock circuit to reduce jitter?
How can I improve my system clock or clock circuit to reduce jitter?
Clock signal jitter or noise can only corrupt the ADC's timing if it exists near the ADC's clock input threshold region. Increasing the clock signal's slew rate shortens its transition time, thereby shortening the time that noise exists during the threshold period. This effectively reduces the rms jitter introduced into the system. For example, a 12-bit ADC that requires a minimum rms jitter of 100 fs for a 70 MHz analog input must have a slew rate of 1 V/ns.
It can be seen that reducing jitter means increasing the slew rate of the clock edge. Here are two methods for reference
Improve the clock source itself. Custom high-performance clock oscillators are often used to characterize the baseline performance achieved by ADI’s ADCs. Not all users of high-speed converters can afford the cost or space requirements of a high-performance, oven-controlled, low-jitter oscillator, but economical oscillators are available that can achieve reasonable performance, even at high input frequencies. Be careful when selecting an “off-the-shelf” oscillator, as oscillator vendors do not always specify or measure jitter in the same way. A practical way to determine which oscillator is most appropriate for a particular application is to collect several oscillators and then test them directly in the system. This can be selected as the only variable for which performance is measured (assuming the oscillator vendor maintains reasonable quality control standards).
Contact the oscillator manufacturer to obtain jitter or phase noise data and recommendations on how to best terminate the device. Improper
oscillator termination can severely degrade the converter’s spurious-free dynamic range (SFDR) performance. Understanding the entire clock system is critical to achieving optimal performance from the converter.
There are many ways to reduce jitter in a system clock circuit, including improving the clock source as discussed above, as well as filtering, frequency division, and selecting the appropriate clock circuit. Be sure to pay attention to the slew rate of the clock, as it will determine the amount of noise that can corrupt the converter during transitions. Minimizing transition times can improve converter performance. Use only the necessary circuitry to drive and distribute the clock, as each component in the signal chain will add to the overall jitter. Finally, do not use "cheap" hardware products, the performance of which may be disappointing. Do not expect top performance from a $70,000 car with $20 tires.
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