STM32MP151A/D
Arm
®
Cortex
®
-A7 800 MHz + Cortex
®
-M4 MPU,
TFT, 35 comm. interfaces, 25 timers, adv. analog
Datasheet
-
production data
Features
LFBGA
TFBGA
Includes ST state-of-the-art patented
technology
Core
•
32-bit Arm
®
Cortex
®
-A7
– L1 32-Kbyte I / 32-Kbyte D
– 256-Kbyte unified level 2 cache
– Arm
®
NEON™ and Arm
®
TrustZone
®
•
32-bit Arm
®
Cortex
®
-M4 with FPU/MPU
– Up to 209 MHz (Up to 703 CoreMark
®
)
LFBGA448 (18 × 18mm)
LFBGA354 (16 × 16mm)
Pitch 0.8mm
TFBGA361 (12 × 12 mm)
TFBGA257 (10 × 10 mm)
min Pitch 0.5mm
•
Low-power modes: Sleep, Stop and Standby
•
DDR memory retention in Standby mode
•
Controls for PMIC companion chip
Low-power consumption
•
Total current consumption down to 2 µA
(Standby mode, no RTC, no LSE, no
BKPSRAM, no RETRAM)
Memories
•
External DDR memory up to 1 Gbyte
– up to LPDDR2/LPDDR3-1066 16/32-bit
– up to DDR3/DDR3L-1066 16/32-bit
•
708 Kbytes of internal SRAM: 256 Kbytes of
AXI SYSRAM + 384 Kbytes of AHB SRAM +
64 Kbytes of AHB SRAM in Backup domain
and 4 Kbytes of SRAM in Backup domain
•
Dual mode Quad-SPI memory interface
•
Flexible external memory controller with up to
16-bit data bus: parallel interface to connect
external ICs and SLC NAND memories with up
to 8-bit ECC
Clock management
•
Internal oscillators: 64 MHz HSI oscillator,
4 MHz CSI oscillator, 32 kHz LSI oscillator
•
External oscillators: 8-48 MHz HSE oscillator,
32.768 kHz LSE oscillator
•
5 × PLLs with fractional mode
General-purpose input/outputs
•
Up to 176 I/O ports with interrupt capability
– Up to 8 secure I/Os
– Up to 6 Wakeup, 3 tampers, 1 active
tamper
Security/safety
•
TrustZone
®
®
peripherals, active tamper
Interconnect matrix
•
2 bus matrices
– 64-bit Arm
®
AMBA
®
AXI interconnect, up to
266 MHz
– 32-bit Arm
®
AMBA
®
AHB interconnect, up
to 209 MHz
•
Cortex -M4 resources isolation
Reset and power management
•
1.71 V to 3.6 V I/Os supply (5 V-tolerant I/Os)
•
POR, PDR, PVD and BOR
•
On-chip LDOs (RETRAM, BKPSRAM, USB
1.8 V, 1.1 V)
•
Backup regulator (~0.9 V)
•
Internal temperature sensors
May 2021
This is information on a product in full production.
3 DMA controllers to unload the CPU
•
48 physical channels in total
•
1 × high-speed general-purpose master direct
memory access controller (MDMA)
DS12500 Rev 6
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www.st.com
STM32MP151A/D
•
2 × dual-port DMAs with FIFO and request
router capabilities for optimal peripheral
management
Up to 25 timers and 3 watchdogs
•
2 × 32-bit timers with up to 4 IC/OC/PWM or
pulse counter and quadrature (incremental)
encoder input
•
2 × 16-bit advanced motor control timers
•
10 × 16-bit general-purpose timers (including 2
basic timers without PWM)
•
5 × 16-bit low-power timers
•
RTC with sub-second accuracy and hardware
calendar
•
4 Cortex
®
-A7 system timers (secure, non-
secure, virtual, hypervisor)
•
1 × SysTick M4 timer
•
3 × watchdogs (2 × independent and window)
Up to 35 communication peripherals
•
6 × I
2
C FM+ (1 Mbit/s, SMBus/PMBus)
•
4 × UART + 4 × USART (12.5 Mbit/s, ISO7816
interface, LIN, IrDA, SPI slave)
•
6 × SPI (50 Mbit/s, including 3 with full duplex
I
2
S audio class accuracy via internal audio PLL
or external clock)
•
4 × SAI (stereo audio: I
2
S, PDM, SPDIF Tx)
•
SPDIF Rx with 4 inputs
•
HDMI-CEC interface
•
MDIO Slave interface
•
3 × SDMMC up to 8-bit (SD /
e•MMC
™
/ SDIO)
•
2 × USB 2.0 high-speed Host
+ 1 × USB 2.0 full-speed OTG simultaneously
– or 1 × USB 2.0 high-speed Host
+ 1 × USB 2.0 high-speed OTG
simultaneously
•
10/100M or Gigabit Ethernet GMAC
– IEEE 1588v2 hardware,
MII/RMII/GMII/RGMII
•
8- to 14-bit camera interface up to 140 Mbyte/s
Hardware acceleration
•
HASH (MD5, SHA-1, SHA224, SHA256),
HMAC
•
2 × true random number generator
(3 oscillators each)
•
2 × CRC calculation unit
Debug mode
•
Arm
®
CoreSight™ trace and debug: SWD and
JTAG interfaces
•
8-Kbyte embedded trace buffer
6 analog peripherals
•
2 × ADCs with 16-bit max. resolution (12 bits
up to 4.5 Msps, 14 bits up to 4 Msps, 16 bits up
to 3.6 Msps)
•
1 × temperature sensor
•
2 × 12-bit D/A converters (1 MHz)
•
1 × digital filters for sigma delta modulator
(DFSDM) with 8 channels/6 filters
•
Internal or external ADC/DAC reference V
REF+
3072-bit fuses including 96-bit unique ID,
up to 1184-bit available for user
All packages are ECOPACK2 compliant
Graphics
•
LCD-TFT controller, up to 24-bit // RGB888
– up to WXGA (1366 × 768) @60 fps or up to
Full HD (1920 × 1080) @30 fps
– Pixel clock up to 90 MHz
– Two layers with programmable colour LUT
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STM32MP151A/D
Contents
Contents
1
2
3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.1
Arm
®
Cortex
®
-A7 subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.1.1
3.1.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.2
3.3
Arm
®
Cortex
®
-M4 with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.3.1
3.3.2
External SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.4
3.5
3.6
3.7
DDR3/DDR3L/LPDDR2/LPDDR3 controller (DDRCTRL) . . . . . . . . . . . . 24
TrustZone address space controller for DDR (TZC) . . . . . . . . . . . . . . . . 25
Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.7.1
3.7.2
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.8
3.9
Low-power strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Reset and clock controller (RCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.9.1
3.9.2
Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
System reset sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.10
3.11
3.12
3.13
3.14
3.15
3.16
3.17
3.18
Hardware semaphore (HSEM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Inter-processor communication controller (IPCC) . . . . . . . . . . . . . . . . . . 31
3.11.1
IPCC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . 32
TrustZone protection controller (ETZPC) . . . . . . . . . . . . . . . . . . . . . . . . . 32
Bus-interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
DMA controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . 35
Extended interrupt and event controller (EXTI) . . . . . . . . . . . . . . . . . . . . 35
Cyclic redundancy check calculation unit (CRC1, CRC2) . . . . . . . . . . . . 36
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Contents
STM32MP151A/D
3.19
3.20
3.21
3.22
3.23
3.24
3.25
3.26
3.27
3.28
3.29
3.30
3.31
3.32
3.33
Flexible memory controller (FMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Dual Quad-SPI memory interface (QUADSPI) . . . . . . . . . . . . . . . . . . . . . 36
Analog-to-digital converters (ADCs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Digital temperature sensor (DTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
V
BAT
operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Digital-to-analog converters (DAC1, DAC2) . . . . . . . . . . . . . . . . . . . . . . . 38
Voltage reference buffer (VREFBUF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Digital filter for sigma delta modulators (DFSDM1) . . . . . . . . . . . . . . . . . 39
Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
LCD-TFT display controller (LTDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
True random number generator (RNG1, RNG2) . . . . . . . . . . . . . . . . . . . 41
Hash processors (HASH1, HASH2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Boot and security and OTP control (BSEC) . . . . . . . . . . . . . . . . . . . . . . . 42
Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.33.1
3.33.2
3.33.3
3.33.4
3.33.5
3.33.6
3.33.7
3.33.8
Advanced-control timers (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . 44
General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM12, TIM13,
TIM14, TIM15, TIM16, TIM17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Basic timers TIM6 and TIM7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Low-power timer (LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5) . . . . . 45
Independent watchdog (IWDG1, IWDG2) . . . . . . . . . . . . . . . . . . . . . . . 45
System window watchdog (WWDG1) . . . . . . . . . . . . . . . . . . . . . . . . . . 45
SysTick timer (Cortex-M4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Generic timers (Cortex-A7 CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.34
3.35
3.36
3.37
3.38
System timer generation (STGEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Real-time clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Tamper and backup registers (TAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Inter-integrated circuit interface (I2C1, I2C2, I2C3, I2C4, I2C5, I2C6) . . . 49
Universal synchronous asynchronous receiver transmitter
(USART1, USART2, USART3, USART6 and UART4, UART5,
UART7, UART8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Serial peripheral interface (SPI1, SPI2, SPI3, SPI4, SPI5,
SPI6)– inter- integrated sound interfaces (I2S1, I2S2, I2S3) . . . . . . . . . . 50
Serial audio interfaces (SAI1, SAI2, SAI3, SAI4) . . . . . . . . . . . . . . . . . . . 51
SPDIF receiver interface (SPDIFRX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.39
3.40
3.41
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Contents
3.42
3.43
3.44
3.45
3.46
3.47
3.48
Management data input/output (MDIOS) . . . . . . . . . . . . . . . . . . . . . . . . . 52
Secure digital input/output MultiMediaCard interface
(SDMMC1, SDMMC2, SDMMC3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Universal serial bus high-speed host (USBH) . . . . . . . . . . . . . . . . . . . . . 52
USB on-the-go high-speed (OTG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Gigabit Ethernet MAC interface (ETH1) . . . . . . . . . . . . . . . . . . . . . . . . . . 54
High-definition multimedia interface (HDMI) – Consumer
electronics control (CEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Debug infrastructure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
4
5
6
Pinouts, pin description and alternate functions . . . . . . . . . . . . . . . . . 56
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
6.1
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
6.1.6
6.1.7
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . 121
6.2
6.3
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.3.6
6.3.7
6.3.8
6.3.9
6.3.10
6.3.11
6.3.12
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . 125
Embedded reset and power control block characteristics . . . . . . . . . . 127
Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Embedded regulators characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 130
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Wakeup time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 141
External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 143
External clock source security characteristics . . . . . . . . . . . . . . . . . . . 149
Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 149
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
PLL spread spectrum clock generation (SSCG) characteristics . . . . . 154
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7
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