Why should a DC-DC converter be placed as close to the load's point-of-load (POL) power supply as possible?

Many of these digital systems use high currents and low voltages, so there is an increased need to keep the distance between the source and the load as short as possible. One obvious problem caused by high currents is that the voltage produced by the line drops continuously from the converter to the load. Figures 1 and 2 show how minimizing the lead resistance between the source and load can minimize the output voltage drop of the converter—in this case, the controller IC and the MOSFET powering the CPU.

Figure 1. DC-DC output voltage drop when PCB traces are narrow

Figure 2. DC-DC output voltage drop when PCB traces are wide

Wider PCB traces shown in Figure 2 reduce voltage drop to meet accuracy requirements, but parasitic inductance must also be considered. The PCB trace length in Figure 2 is estimated to have an inductance of approximately 14.1 nh, as shown in the LTspice® ^model in Figure 3 .

Figure 3. LTspice model of PCB trace inductance

The inductor will suppress the dynamic change of current di/dt. When the load changes, the current passing through the parasitic inductor is limited by its time constant, and the transient response is degraded. The result of parasitic inductance is a voltage drop, as shown in the simulation diagram in Figure 4.

Figure 4. DC-DC output voltage sag and transient current

Placing the converter close to the load minimizes the effects of PCB resistance and parasitic inductance. The DC-DC converter IC should be placed closest to the CPU. Note that Figures 1 and 2 show the schematics of a conventional high-current power supply (i.e., switch-mode controller and external FETs). Controller FET solutions can handle the high current loads required for the above applications. The problem with the controller solution is that there are space requirements for the external FET, so it may be difficult to obtain a true POL regulator solution, as shown in the example layout in Figure 5.

Figure 5. Ideal layout of DC-DC converter and CPU

An alternative to the controller is a single-chip solution where the FET is inside the converter IC. For example, the LTC3310S monolithic buck regulator (IC size is 3 mm × 3 mm) enables a point-of-load solution that can deliver up to 10 A from a single IC or 20 A from multiple ICs in parallel. These ICs are shown in Figure 6 and Figure 12 respectively.

Figure 6. LTC3310S Buck Regulator

Figure 7. Small size LTC3310S supports POL layout

In addition to its small package size, the LTC3310S supports switching frequencies up to 5 MHz—high-frequency operation reduces necessary output capacitance and overall solution PCB size. Figure 8 shows the load transient performance of the LTC3310S, where the output voltage shift caused by an 8 A load change is less than ±40 mV, and only 110μF output capacitance is required to achieve this performance.

Figure 8. Transient response of LTC3310S

Although there are clear advantages to using high-power monolithic POL converters, there is one factor that may be a spoiler: heat. If the converter generates too much heat, it will not be useful in an already hot system.

In the above solution, the LTC3310S internal temperature rise is minimized through high-efficiency operation, allowing it to operate reliably even under harsh temperature conditions surrounding high-power devices such as CPUs, SoCs, and FPGAs. In addition, LTC3310S has a built-in precision temperature sensor that supports measuring the internal junction temperature through the SSTT pin, as shown in Figure 10, and the corresponding temperature sensor characteristics are shown in Figure 11.

Figure 9. Thermal camera image of LTC3310S

Figure 10. LTC3310S temperature detection pin

Figure 11. Soft-start and temperature monitoring operation

Some monolithic regulators can be scaled to higher load applications through multiphase parallel operation. Figure 12 shows multiple LTC3310S devices operating in parallel and out of phase, doubling the current capability.

The controller's clock is set by a single resistor on the RT pin, and the relative phases of the child nodes are programmed through a resistor divider on the RT pin. In the case shown in Figure 12, RT is grounded, setting the subnodes 180° phase shifted relative to the controller.

Figure 12.20 A two-phase monolithic regulator POL solution

Figure 13 shows the inductor current and output ripple current of the 2-channel converter, as shown in Figure 12. In-phase performance is compared to dual-inverting performance. Inverting operation reduces the output ripple current (through cancellation) from 14 A peak-to-peak (single-phase) to 6 A peak-to-peak (biphase) without the need for additional external filters.

Figure 13. Comparison of inductor current and output current of two versions of a dual-channel converter: (a) non-inverting channel versus (b) inverting channel

In short, the LTC3310S is an efficient and small POL solution suitable for high-current power systems that power power-hungry CPUs, SoCs, and FPGAs. Their small size and optimized power efficiency result in low self-heating, allowing them to be placed very close to the load. It can be easily paralleled to increase power using multiple LTC3310S in a multiphase solution.

View previous content↓↓↓