What exactly is an interleaved ADC? Today we will give you a brief introduction~

First, it is important to understand exactly what an interleaved ADC is. To understand interleaving, it is best to understand what is actually happening and how it is achieved. With this basic understanding, the benefits of interleaving can then be discussed. Of course, as we all know, there is no such thing as a free lunch, so the technical challenges associated with interleaved sampling need to be fully evaluated and verified.

If the ADCs are interleaved, two or more ADCs with a fixed clock phase difference relationship are used to synchronously sample the input signal and produce a combined output signal that can sample bandwidths that are multiples of the bandwidth of a single ADC. Using m ADCs increases the effective sampling rate by a factor of m. For simplicity and ease of understanding, we focus on the case of two ADCs. In this case, if the two ADCs each have a sampling rate of f _S and are interleaved, the final sampling rate is 2× f _S . The two ADCs must have a defined clock phase difference relationship in order to interleave correctly. The clock phase relationship is given by Equation 1, where n is a specific ADC and m is the total number of ADCs.

For example, if both ADCs sample at 100 MSPS and are interleaved, the sampling rate is 200 MSPS. In this case, Equation 1 can be used to derive the clock phase relationship of the two ADCs, as shown in Equation 2 and Equation 3.

Note that if the clock phase relationship is known, the combined outputs for different quantized values ​​can be determined. Figure 1 graphically illustrates the clock phase relationship and sample structure of two 100 MSPS interleaved ADCs. Note the 180° clock phase relationship and how the samples are interleaved. The input waveform can also be sampled by two ADCs. In this case, interleaving is achieved using a 200 MHz clock input divided by 2 and the desired clock phase sent to each ADC.

This concept can be expressed in another way, as shown in Figure 2. By combining these two 100MSPS ADCs in an interleaved fashion, the sampling rate can be increased to 200 MSPS. This allows each Nyquist zone to be extended from 50 MHz to 100 MHz, doubling the available bandwidth for operation. The increased operating bandwidth provides many benefits for applications in multiple market sectors. Radio systems can increase the number of frequency bands they support; radar systems can increase spatial resolution; and measurement equipment can achieve higher analog input bandwidths.

The benefits of interleaving can benefit multiple market segments. The biggest benefit of interleaved ADCs is increased bandwidth because the Nyquist bandwidth of the ADC is wider. Again, let’s take the example of two 100 MSPS ADCs interleaved to achieve a 200 MSPS sampling rate. Figure 3 shows that by interleaving the two ADCs, the bandwidth can be greatly increased. This has many benefits for multiple application scenarios. Just as cellular standards have increased channel bandwidth and the number of operating frequency bands, the requirements for the available bandwidth of ADCs have also increased. In addition, in military applications, the need for better spatial discrimination and increased channel bandwidth for back-end communications have required ADCs to provide higher bandwidth. As bandwidth requirements in these areas increase, so do the needs to accurately measure these signals. Therefore, in order to correctly acquire and measure these high bandwidth signals, the measurement equipment also needs higher bandwidth. In many designs, the system requirements are actually ahead of commercial ADC technology. Interleaving can bridge this technology gap.

Increasing the sampling rate provides more bandwidth for these applications, making frequency planning easier and reducing the complexity and cost of anti-aliasing filters that are typically used at the ADC input. With all these benefits, one must wonder what the price is. As with most things, there is no such thing as a free lunch. Interleaved ADCs offer higher bandwidth and other useful benefits, but they also present some challenges when dealing with interleaved ADCs.

There are some challenges and some considerations when interleaving ADCs. Due to imperfections associated with interleaving ADCs, spurs will appear in the output spectrum. These imperfections are basically mismatches between the two ADCs being interleaved. There are four basic mismatches that are caused by spurs in the output spectrum. These include offset mismatch, gain mismatch, timing mismatch, and bandwidth mismatch.

Perhaps the easiest of these to understand is the offset mismatch between the two ADCs. Each ADC will have an associated dc offset value. When the two ADCs are interleaved and the sampling alternates back and forth between the two ADCs, the dc offset of each successive sample will change. Figure 4 illustrates how each ADC has its own dc offset and how the interleaved output effectively switches back and forth between these two dc offset values. The output switches between these offset values ​​at a rate of f _{S /2, which will result in a spur in the output spectrum located at f S} /2. Since the mismatch itself has no frequency component and is only dc, the frequency of the spur that appears in the output spectrum depends only on the sampling frequency and will always appear at f _S /2. The magnitude of the spur depends on the magnitude of the offset mismatch between the ADCs. The greater the mismatch, the greater the spur value. To minimize the spur caused by the offset mismatch, it is not necessary to completely eliminate the dc offset in each ADC. Doing so would filter out all of the dc content in the signal and is not suitable for systems using a zero-IF (ZIF) architecture where the signal components are complex and the dc content is actually the signal of interest. Instead, a more appropriate technique is to match the offset of one of the ADCs to the other. The offset of one ADC is chosen as the reference, and the offset of the other ADC is set to a value as close as possible. The closer the offset values ​​are matched, the lower the spurious value generated at f _{S /2.}

The second mismatch to watch out for when interleaving is the gain mismatch between the ADCs. Figure 5 shows the gain mismatch between two interleaved converters. In this case, there is a mismatch frequency component. In order to observe this mismatch, a signal must be applied to the ADCs. For offset mismatch, no signal is needed to see the inherent dc offset of the two ADCs. For gain mismatch, if no signal is present, the gain mismatch cannot be measured and therefore cannot be understood. Gain mismatch will produce output spectrum spurs that are related to the input frequency and sampling rate and appear at f _S /2 ± f _IN . To minimize the spurs caused by gain mismatch, a similar strategy is used as for offset mismatch. The gain of one of the ADCs is chosen as the reference and the gain of the other ADC is set to a value as close as possible. The closer the gain values ​​of each ADC are matched, the smaller the spurs produced in the output spectrum.

Next, we must explore the timing mismatch between the two ADCs. Timing mismatch has two components: group delay in the analog portion of the ADC and clock phase deviation. The analog circuitry in the ADC has an associated group delay, and the group delay value of the two ADCs may be different. In addition, there is clock skew, which also has two components: the aperture uncertainty of each ADC and a component related to the phase accuracy of the clock input to each converter. Figure 6 graphically illustrates the mechanism and effects of ADC timing mismatch. Similar to the gain mismatch spur, the timing mismatch spur is also a function of the input frequency and sampling rate, appearing at f _S /2 ± f _IN .

To minimize the spurs caused by timing mismatch, the group delay of the analog sections of each converter needs to be properly matched using appropriate circuit design techniques. In addition, the clock path design must be as consistent as possible to minimize the difference in aperture uncertainty. Finally, the clock phase relationship must be precisely controlled so that the two input clocks are as close as possible to 180° apart. As with other mismatches, the goal is to minimize the mechanism that causes the timing mismatch.

The final mismatch is perhaps the most difficult to understand and deal with: bandwidth mismatch. As shown in Figure 7, bandwidth mismatch has both gain and phase/frequency components. This makes solving bandwidth mismatch more difficult because it has components of the other two mismatch parameters. However, in bandwidth mismatch, we see different gain values ​​at different frequencies. In addition, bandwidth has a timing component, causing signals at different frequencies to experience different delays as they pass through each converter. Good circuit design and layout practices are the best way to reduce bandwidth mismatch between ADCs. The better the match between ADCs, the fewer spurs that are generated. Just as gain and timing mismatches result in spurs at f _S /2 ± f _IN in the output spectrum, bandwidth mismatches can also result in spurs at the same frequencies.

Now that we have discussed the four different mismatches that cause problems when interleaving ADCs, one commonality can be seen. Three of the four mismatches will produce spurs at f _S /2 ± f _IN in the output spectrum . The offset mismatch spur is easy to identify because it is the only one located at f _S /2 and can be easily compensated for. Gain, timing, and bandwidth mismatches will all produce spurs at f _S /2 ± f _IN in the output spectrum ; therefore, the question then becomes: how to determine their respective contributions. Figure 8 provides a simple graphical guide to identifying the sources of spurs from the different mismatches in an interleaved ADC.

If you are only looking at gain mismatch, it is a low frequency (or DC) type of mismatch. By performing a low frequency gain measurement near DC and then performing a gain measurement at a higher frequency, you can separate the gain component of the bandwidth mismatch from the gain mismatch. Gain mismatch is not a function of frequency, while the gain component of the bandwidth mismatch is a function of frequency. A similar approach can be taken for timing mismatch. Perform a low frequency measurement near DC and then perform a subsequent measurement at a higher frequency to separate the timing component of the bandwidth mismatch from the timing mismatch.

The latest communications system designs, cutting-edge radar technology, and ultra-high bandwidth measurement equipment seem to always be ahead of existing ADC technology. Driven by these demands, users and manufacturers of ADCs are trying to keep up with the pace of these demands. Interleaving ADCs can achieve wider bandwidths faster than the traditional way of increasing the conversion rate of typical ADCs. Interleaving two or more ADCs can increase the available bandwidth and meet system design requirements more quickly. However, interleaving ADCs does not come without a price, and mismatches between ADCs cannot be ignored. While mismatches do exist, understanding their nature and how to properly deal with them will enable designers to more intelligently utilize these interleaved ADCs and meet the growing requirements of the latest system designs.